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Equator Hardware Reference
MAP-CA DSP Datasheet
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Equator Technologies, Inc.
June 20, 2001 Document Number: HWR.CA.DS.2001.06.20
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Equator Hardware Reference MAP-CA DSP Datasheet
June 20, 2001
Copyright © 2000 - 2001 Equator Technologies, Inc., and Hitachi, Ltd.
Equator makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes no commitment to update the information contained herein. Equator reserves the right to change or discontinue this product at any time, without notice. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on information in this document. The following are trademarks of Equator Technologies, Inc., and may be used to identify Equator products only: Equator, MAP, MAP1000, MAP1000A, MAP-CA, MAP Series, Broadband Signal Processor, BSP, FIRtree, DataStreamer, DS, iMMediaC, iMMediaTools, iMMediaToolsLite, Media Intrinsics, VersaPort, SofTV, StingRay, Equator Around, and the Equator Around logo. Other product and company names contained herein may be trademarks of their respective owners. The MAP-CA digital signal processor was jointly developed by Equator Technologies, Inc., and Hitachi, Ltd. DataSheet4U.com
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Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001
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MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd.
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Table of Contents
Introduction to the MAP-CA Digital Signal Processor Chip ..........................................xi Chapter 1 Architecture Overview .......................................................................................... 1
1.1 The VLIW Core.................................................................................................................... 2 1.1.1 Execution Units............................................................................................................. 2 1.1.1.1 I-ALU.................................................................................................................... 3 1.1.1.2 IG-ALU ................................................................................................................. 3 1.1.1.3 Simple Interlocks .................................................................................................. 3 1.1.1.4 Extensive Predication............................................................................................ 3 1.1.2 Register Resources........................................................................................................ 3 1.1.2.1 Global Registers .................................................................................................... 3 1.1.2.2 Breakpoint Registers ............................................................................................. 3 1.1.2.3 General Registers .................................................................................................. 3 1.1.2.4 Predicate Registers ................................................................................................ 3 1.1.2.5 PLC/PLV 128-bit registers.................................................................................... 4 DataSheet4U.com 1.2 Interrupts and Exceptions ..................................................................................................... 4 1.2.1 Core Interrupts and Exceptions..................................................................................... 4 1.2.2 Interrupt Controller ....................................................................................................... 4 1.3 Timers................................................................................................................................... 5 1.4 Memory Hierarchy ............................................................................................................... 5 1.4.1 Caches..................