TC74AC112FN

www.DataSheet4U.com TC74AC112P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC112P,TC74AC112F,TC74AC112FN Dual J-K Flip Flop with Preset and Clear Note: The TC74AC112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. In accordance with the logic level given J and K input this device changes state on negative going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage. xxxFN (JEDEC SOP) is not available in Japan. TC74AC112P TC74AC112F Features High speed: fmax = 170 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 4 µA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω DataShee DataSheet4U.com transmission lines. ∼ tpHL Balanced propagation delays: tpLH − Wide operating voltage range: VCC (opr) = 2 to 5.5 V Pin and function compatible with 74F112 Pin Assignment TC74AC112FN Weight DIP16-P-300-2.54A SOP16-P-300-1.27A SOP16-P-300-1.27 SOL16-P-150-1.27 : 1.00 g (typ.) : 0.18 g (typ.) : 0.18 g (typ.) : 0.13 g (typ.) DataSheet4U.com 1 Data...