PPC405GP

www.DataSheet4U.com Part Number 405GP Revision 2.01 – January 6, 2005 405GP Features Data Sheet Power PC 405GP Embedded Processor PowerPC® 405 32-bit RISC processor core operating up to 266MHz Synchronous DRAM (SDRAM) interface operating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications 4KB on-chip memory (OCM) External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Synchronous or asynchronous PCI Bus interface - Internal or external PCI Bus Arbiter Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII) Programmable interrupt controller supports seven external and 19 internal edge triggered or levelsensitive interrupts Programmable timers Two serial ports (16550 compatible UART) One IIC interface General purpose I/O (GPIO) available DataSheet4U.com Supports JTAG for board level testing Internal processor local Bus (PLB) runs at SDRAM interface frequency Supports PowerPC processor boot from PCI memory DataShee DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels Description Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP) provides a high-performance, lo...