EDS1216AATA

www.DataSheet4U.com DATA SHEET 128M bits SDRAM EDS1216AATA (8M words × 16 bits) Description The EDS1216AATA is a 128M bits SDRAM organized as 2,097,152 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 54-pin plastic TSOP (II). Pin Configurations /xxx indicate active low signal. 54-pin Plastic TSOP (II) VDD DQ0 VDDQ Features 3.3V power supply Clock frequency: 133MHz (max.) Single pulsed /RAS ×16 organization 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length (BL): 1, 2, 4, 8, full page 2 variations of burst sequence  Sequential (BL = 1, 2, 4, 8, full page)  Interleave (BL = 1, 2, 4, 8) Programmable /CAS latency (CL): 2, 3 Byte control by UDQM and LDQM Refresh cycles: 4096 refresh cycles/64ms 2 variations of refresh  Auto refresh  Self refresh TSOP (II) package with lead free solder (Sn-Bi) DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ (Top view) ww.DataSheet4U.com A0 to A11 BA0, BA1 DQ0 to DQ15 /CS /RAS /CAS /WE LDQM, UDQM CKE CLK VDD VSS VDDQ VSSQ NC Address input Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable Input/output mask Clock enable Clock input Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection Document No. E0411E40 (Ver. 4.0) Date Published ...