DatasheetsPDF.com

TC74LVX02FT Dataheets PDF



Part Number TC74LVX02FT
Manufacturers Toshiba Semiconductor
Logo Toshiba Semiconductor
Description Quad 2-Input NOR Gate
Datasheet TC74LVX02FT DatasheetTC74LVX02FT Datasheet (PDF)

TC74LVX02F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LVX02F, TC74LVX02FT Quad 2-Input NOR Gate The TC74LVX02F/FT is a high-speed CMOS 2-input NOR gate fabricated with silicon gate CMOS technology. Designed for use in 3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. This device is suitable for low-voltage and battery operated systems. The internal circuit is composed of 3 stages including buffer output, which provide high noi.

  TC74LVX02FT   TC74LVX02FT


Document
TC74LVX02F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LVX02F, TC74LVX02FT Quad 2-Input NOR Gate The TC74LVX02F/FT is a high-speed CMOS 2-input NOR gate fabricated with silicon gate CMOS technology. Designed for use in 3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. This device is suitable for low-voltage and battery operated systems. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. An input protection circuit ensures that 0 to 5.5V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features • High-speed: tpd = 4.5 ns (typ.) (VCC = 3.3 V) • Low-power dissipation: ICC = 2 μA (max) (Ta = 25°C) • Input voltage level: VIL = 0.8 V (max) (VCC = 3 V) VIH = 2.0 V (min) (VCC = 3 V) • Power-down protection provided on all inputs • Balanced propagation delays: tpLH ∼− tpHL • Low noise: VOLP = 0.5 V (max) • Pin and function compatible with 74HC02 TC74LVX02F TC74LVX02FT Weight SOP14-P-300-1.27A TSSOP14-P-0044-0.65A : 0.18 g (typ.) : 0.06 g (typ.) Start of commercial production 1993-01 1 2014-03-01 Pin Assignment (top view) 1Y 1 1A 2 1B 3 2Y 4 2A 5 2B 6 GND 7 14 VCC 13 4Y 12 4B 11 4A 10 3Y 9 3B 8 3A TC74LVX02F/FT IEC Logic Symbol (2) 1A (3) 1B (5) 2A (6) 2B (8) 3A (9) 3B (11) 4A (12) 4B >1 (1) 1Y (4) 2Y (10) 3Y (13) 4Y Truth Table Inputs A B L L L H H L H H Outputs Y H L L L Absolute Maximum Ratings (Note) Characteristics Symbol Rating Unit Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature VCC VIN VOUT IIK IOK IOUT ICC PD Tstg −0.5 to 7.0 V −0.5 to 7.0 V −0.5 to VCC + 0.5 V −20 mA ±20 mA ±25 mA ±50 mA 180 mW −65 to 150 °C Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 2 2014-03-01 TC74LVX02F/FT Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time VCC VIN VOUT Topr dt/dv 2.0 to 3.6 0 to 5.5 0 to VCC −40 to 85 0 to 100 V V V °C ns/V Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Electrical Characteristics DC Characteristics Characteristics Input voltage H-level L-level H-level Output voltage L-level Input leakage current Quiescent supply current Symbol Test Condition Ta = 25°C Ta = −40 to 85°C Unit VCC (V) Min Typ. Max Min Max 2.0 1.5 ⎯ ⎯ 1.5 ⎯ VIH ⎯ 3.0 2.0 ⎯ ⎯ 2.0 ⎯ 3.6 2.4 ⎯ ⎯ 2.4 ⎯ V 2.0 ⎯ ⎯ 0.5 ⎯ 0.5 VIL ⎯ 3.0 ⎯ ⎯ 0.8 ⎯ 0.8 3.6 ⎯ ⎯ 0.8 ⎯ 0.8 IOH = −50 μA 2.0 1.9 2.0 ⎯ 1.9 ⎯ VOH VIN = VIL IOH = −50 μA 3.0 2.9 3.0 ⎯ 2.9 ⎯ IOH = −4 mA 3.0 2.58 ⎯ ⎯ 2.48 ⎯ V IOL = 50 μA 2.0 ⎯ 0 0.1 ⎯ 0.1 VOL VIN = VIH or VIL IOL = 50 μA 3.0 ⎯ 0 0.1 ⎯ 0.1 IOL = 4 mA 3.0 ⎯ ⎯ 0.36 ⎯ 0.44 IIN VIN = 5.5 V or GND 3.6 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA ICC VIN = VCC or GND 3.6 ⎯ ⎯ 2.0 ⎯ 20.0 μA 3 2014-03-01 TC74LVX02F/FT AC Characteristics (input: tr = tf = 3 ns) Characteristics Propagation delay time Symbol Test Condition Ta = 25°C Ta = −40 to 85°C Unit VCC (V) CL (pF) Min Typ. Max Min Max 15 ⎯ 5.9 10.7 1.0 13.5 tpLH ⎯ 2.7 50 ⎯ 8.4 14.2 1.0 17.0 ns 15 ⎯ 4.5 6.6 1.0 8.0 tpHL 3.3 ± 0.3 50 ⎯ 7.0 10.1 1.0 11.5 Output to output skew Input capacitance Power dissipation capacitance tosLH tosHL CIN CPD 2.7 50 ⎯ ⎯ 1.5 ⎯ 1.5 (Note 1) ns 3.3 ± 0.3 50 ⎯ ⎯ 1.5 ⎯ 1.5 (Note 2) ⎯ 4 10 ⎯ 10 pF (Note 3) ⎯ 15 ⎯ ⎯ ⎯ pF Note 1: Parameter guaranteed by design. (tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|) Note 2: Parameter guaranteed by design. Note 3: CPD is defined as the value of the internal equivalent capacitance which is ca.


TC74LVX02F TC74LVX02FT TC74LVX04F


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)