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ICS252 Dataheets PDF



Part Number ICS252
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Field Programmable Dual Output SS VersaClock Synthesizer
Datasheet ICS252 DatasheetICS252 Datasheet (PDF)

www.DataSheet4U.com ICS252 Field Programmable Dual Output SS VersaClock Synthesizer Description The ICS252 is a low cost, dual-output, field programmable clock synthesizer. The ICS252 can generate two output frequencies from 314 kHz to 200 MHz using up to two independently configurable PLLs. The outputs may employ Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). Using ICS’ VersaClock software to configure the PLL and output, the ICS252 contains a One-Time Program.

  ICS252   ICS252



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www.DataSheet4U.com ICS252 Field Programmable Dual Output SS VersaClock Synthesizer Description The ICS252 is a low cost, dual-output, field programmable clock synthesizer. The ICS252 can generate two output frequencies from 314 kHz to 200 MHz using up to two independently configurable PLLs. The outputs may employ Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). Using ICS’ VersaClock software to configure the PLL and output, the ICS252 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include 4 selectable configuration registers. The device employs Phase-Locked Loop (PLL) techniques to run from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The device also has a power-down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. The ICS252 is also available in factory programmed custom versions for high-volume applications. ™ Features • • • • • • • • • • • 8-pin SOIC package Two addressable registers Input crystal frequency of 5 to 27 MHz Clock input frequency of 3 to 150 MHz Output clock frequencies up to 200 MHz Configurable Spread Spectrum Modulation Operating voltage of 3.3 V Replaces multiple crystals and oscillators Controllable output drive levels Advanced, low-power CMOS process Available in Pb (lead) free packaging www.DataSheet4U.com VDD Block Diagram SEL OTP ROM with PLL Values PLL1 Divide Logic and Output Enable Control CLK1 CLK2 PLL2 X1 Crystal X2 External capacitors are required. GND Crystal Oscillator PDTS MDS 252 B Integrated Circuit Systems, Inc. ● 1 525 Race Street, San Jose, CA 95126 ● Revision 011606 tel (408) 297-1201 ● www.icst.com www.DataSheet4U www.DataSheet4U.com 4U.com www.DataSheet4U.com ICS252 Field Programmable Dual Output SS VersaClock Synthesizer Pin Assignment SEL VDD X1/ICLK X2 1 2 3 4 8 7 6 5 PDTS GND CLK2 CLK1 Output Clock Selection Table S1 0 0 CLK1 (MHz) User Configurable User Configurable CLK2 (MHz) User Configurable User Configurable Spread Percentage User Configurable User Configurable 8-pin (150 mil) SOIC Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 Pin Name SEL VDD X1/ICLK X2 CLK1 CLK2 GND PDTS Pin Type Input Power XI XO Output Input Power Input Connect to +3.3 V. Pin Description Select pin for frequency selection on CLK1 and CLK2. Internal pull-up resistor. Connect this pin to a crystal or external clock input. Connect this pin to a crystal, or float for clock input. Clock1 output. Weak internal pull-down when tri-stated. Clock2 output. Weak internal pull-down when tri-stated. Connect this to ground. Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up resistor. www.DataSheet4U.com Crystal Load Capacitors External Components The ICS252 requires a minimum number of external components for proper operation. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS252 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and the PCB ground plane. MDS 252 B Integrated Circuit Systems, Inc. ● 2 525 Race Street, San Jose, CA 95126 ● Revision 011606 tel (408) 297-1201 ● www.icst.com www.DataSheet4U www.DataSheet4U.com 4U.com www.DataSheet4U.com ICS252 Field Programmable Dual Output SS VersaClock Synthesizer PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk.


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