DM81LS95A

www.DataSheet4U.com DM81LS95A DM81LS96A DM81LS97A 3-STATE Octal Buffer September 1991 Revised May 1999 DM81LS95A DM81LS96A DM81LS97A 3-STATE Octal Buffer General Description These devices provide eight, two-input buffers in each package. All employ low-power-Schottky TTL technology. One of the two inputs to each buffer is used as a control line to gate the output into the high-impedance state, while the other input passes the data through the buffer. The DM81LS95A and DM81LS97A present true data at the outputs, while the DM81LS96A is inverting. On the DM81LS95A and DM81LS96A versions, all eight 3-STATE enable lines are common, with access through a 2-input NOR gate. On the DM81LS97A version, four buffers are enabled from one common line, and the other four buffers are enabled form another common line. In all cases the outputs are placed in the 3-STATE condition by applying a high logic level to the enable pins. Features s Typical power dissipation DM81LS95A, DM81LS97A DM81LS96A s Typical propagation delay DM81LS95A, DM81LS97A DM81LS96A 15 ns 10 ns 80 mW 65 mW s Low power-Schottky, 3-STATE technology Ordering Code: Order Number DM81LS95AN DM81LS96AN DM81LS97AN DM81LS95AWM DM81LS96AWM www.DataSheet4U.com Package Number M20B N20A N20A N20A M20B Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.30...