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ADVANCED INFORMATION
MX29LV401T/B
4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V • 524,288 x 8/262,144 x 16 switchable • Single power supply operation - 3.0V only operation for read, erase and program operation • Fast access time: 55R/70/90ns • Low power consumption - 20mA maximum active current - 0.2uA typical standby current • Command register architecture - Byte/word Programming (9us/11us typical) - Sector Erase (Sector structure 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7) • Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address • Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase. • Status Reply - Data polling & Toggle bit for detection of program and erase operation completion. • Ready/Busy pin (RY/BY) - Provides a hardware method of detecting program or erase operation completion. • Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Tempoary sector unprotect allows code changes in previously locked sectors. • 100,000 minimum erase/program cycles • Latch-up protected to 100mA from -1V to VCC+1V • Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector • Low VCC write inhibit is equal to or less than 2.3V • Package type: - 44-pin SOP - 48-pin TSOP - 48-ball CSP • Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash
GENERAL DESCRIPTION
The MX29LV401T/B is a 4-mega bit Flash memory organized as 512K bytes of 8 bits or 256K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV401T/B is packaged in 44-pin SOP, 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV401T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV401T/B has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV401T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29LV401T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
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REV. 0.0, SEP. 14, 2001
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MX29LV401T/B
PIN CONFIGURATIONS PIN DESCRIPTION
44 SOP(500 mil)
NC RY/BY A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
SYMBOL A0~A17 Q0~Q14 Q15/A-1 CE WE BYTE RESET OE RY/BY VCC GND
PIN NAME Address Input Data Input/Output Q15(Word mode)/LSB addr(Byte mode) Chip Enable Input Write Enable Input Word/Byte Selction input Hardware Reset Pin/Sector Protect Unlock Output Enable Input Ready/Busy Output Power Supply Pin (2.7V~3.6V) Ground Pin
48 TSOP (Standard Type) (12mm x 20mm)
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RSEET NC NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0
MX29LV401T/B
MX29LV401T/B
48-Ball CSP (6mm x 8mm, Ball Pitch = 0.8 mm), Top View, Balls Facing Down A 6 5 4 3 2 A13 A9 B A12 A8
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E A16 Q7 Q5 Q2 Q0 A0
F BYTE Q14 Q12 Q10 Q8 CE
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Q15/A-1 GND Q13 Vcc Q11 Q9 OE Q6 Q4 Q3 Q1 GND
REV. 0.0, SEP. 14, 2001
RESET
P/N:PM0853
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MX29LV401T/B
BLOCK STRUCTURE Table 1: MX29LV401T SECTOR ARCHITECTURE
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA.