EPF6000

www.DataSheet4U.com FLEX 6000 ® Programmable Logic Device Family Data Sheet March 2001, ver. 4.1 Features... s s s Provides an ideal low-cost, programmable alternative to highvolume gate array applications and allows fast design changes during prototyping or design testing Product features – Register-rich, look-up table- (LUT-) based architecture – OptiFLEX® architecture that increases device area efficiency – Typical gates ranging from 5,000 to 24,000 gates (see Table 1) – Built-in low-skew clock distribution tree – 100% functional testing of all devices; test vectors or scan chains are not required System-level features – In-circuit reconfigurability (ICR) via external configuration device or intelligent controller – 5.0-V devices are fully compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic – MultiVoltTM I/O interface operation, allowing a device to bridge between systems operating at different voltages – Low power consumption (typical specification less than 0.5 mA in standby mode) – 3.3-V devices support hot-socketing Table 1. FLEX 6000 Device Features Feature Typical gates (1) Logic elements (LEs) Maximum I/O pins Supply voltage (VCCINT) Note: (1) EPF6010A 10,000 880 EPF6016 16,000 1,320 204 5.0 V EPF6016A 16,000 1,320 171 ...