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TS80L188EC Dataheets PDF



Part Number TS80L188EC
Manufacturers Intel
Logo Intel
Description 16-Bit High Integration Embedded Processors
Datasheet TS80L188EC DatasheetTS80L188EC Datasheet (PDF)

www.DataSheet4U.com 80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent DMA Channels 22 Multiplexed I O Port Pins Two 8259A Compatible Programmable Interrupt Controllers Three Programmable 16-Bit Timer Counters 32-Bit Watchdog Timer Ten Programmable .

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www.DataSheet4U.com 80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent DMA Channels 22 Multiplexed I O Port Pins Two 8259A Compatible Programmable Interrupt Controllers Three Programmable 16-Bit Timer Counters 32-Bit Watchdog Timer Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit Power Management Unit On-Chip Oscillator System Level Testing Support (ONCE Mode) Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Low-Power Operating Modes Idle Mode Freezes CPU Clocks but Keeps Peripherals Active Powerdown Mode Freezes All Internal Clocks Powersave Mode Divides All Clocks by Programmable Prescalar Y Available in Extended Temperature Range ( b 40 C to a 85 C) Supports 80C187 Numerics Processor Extension (80C186EC only) Package Types 100-Pin EIAJ Quad Flat Pack (QFP) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Shrink Quad Flat Pack (SQFP) Speed Versions Available (5V) 25 MHz (80C186EC25 80C188EC25) 20 MHz (80C186EC20 80C188EC20) 13 MHz (80C186EC13 80C188EC13) Speed Version Available (3V) 16 MHz (80L186EC16 80L188EC16) 13 MHz (80L186EC13 80L188EC13) Y Y Y Y Y Y The 80C186EC is a member of the 186 Integrated Processor Family The 186 Integrated Processor Family incorporates several different VLSI devices all of which share a common CPU architecture the 8086 8088 The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic silicon die www.DataSheet4U.com Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT © INTEL CORPORATION, 2004 August, 2004 Order Number: 272434-006 www.DataSheet4U.com 80C186EC 80C188EC and 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR CONTENTS INTRODUCTION 80C186EC CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Programmable Interrupt Controllers Timer Counter Unit Serial Communications Unit DMA Unit Chip-Select Unit I O Port Unit Refresh Control Unit Watchdog Timer Unit Power Management Unit 80C187 Interface (80C186EC only) ONCE Test Mode PACKAGE INFORMATION Prefix Identification Pin Descriptions Pinout Package Thermal Specifications ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PAGE 4 4 4 4 5 7 7 7 7 7 7 7 7 8 8 8 8 8 8 15 24 25 25 CONTENTS Recommended Connections DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation AC SPECIFICATIONS AC Characteristics 80C186EC25 AC Characteristics 80C186EC20 13 AC Characteristics 80L186EC13 AC Characteristics 80L186EC16 Relative Timings Serial Port Mode 0 Timings AC TEST CONDITIONS AC TIMING WAVEFORMS DERATING CURVES RESET BUS CYCLE WAVEFORMS EXECUTION TIMINGS INSTRUCTION SET SUMMARY ERRATA REVISION HISTORY PAGE 25 26 29 29 30 30 32 33 34 35 36 37 37 40 40 43 50 51 57 57 www.DataSheet4U.com 2 80C186EC 188EC 80L186EC 188EC www.DataSheet4U.com 272434 – 1 NOTE Pin names in parentheses apply to the 80C188EC 80L188EC www.DataSheet4U.com Figure 1 80C186EC 80L186EC Block Diagram 3 80C186EC 188EC 80L186EC 188EC www.DataSheet4U.com INTRODUCTION Unless specifically noted all references to the 80C186EC apply to the 80C188EC 80L186EC and 80L188EC References to pins that differ between the 80C186EC 80L186EC and the 80C188EC 80L188EC are given in parentheses The ‘‘L’’ in the part number denotes low voltage operation Physically and functionally the ‘‘C’’ and ‘‘L’’ devices are identical The 80C186EC is one of the highest integration members of the 186 Integrated Processor Family Two serial ports are provided for services such as interprocessor communication diagnostics and modem interfacing Four DMA channels allow for high speed data movement as well as support of the onboard serial ports A flexible chip select unit simplifies memory and peripheral interfacing The three general purpose timer counters can be used for a variety of time measurement and waveform generation tasks A watchdog timer is provided to insure system integrity even in the most hostile of environments Two 8259A compatible interrupt controllers handle internal interrupts and up to 57 external interrupt requests A DRAM refresh unit and 24 multiplexed I O ports round out the feature set of the 8.


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