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ICS574 Dataheets PDF



Part Number ICS574
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Zero Delay Low Skew Buffer
Datasheet ICS574 DatasheetICS574 Datasheet (PDF)

www.DataSheet4U.com ICS574 Zero Delay, Low Skew Buffer Description The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on ICS’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connecte.

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www.DataSheet4U.com ICS574 Zero Delay, Low Skew Buffer Description The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on ICS’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element. ICS manufactures the largest variety of clock generators and buffers, and is the largest clock supplier in the world. Features • Packaged in 8 pin narrow SOIC • Zero input-to-output delay • Four 1X outputs • Output to output skew is less than 150 ps • Output clocks up to 160 MHz at 3.3 V • External feedback path for output edge placement • Spread Smart™ technology works with spread spectrum clock generators • Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V • Advanced, low power, sub-micron CMOS process • Operating voltage from 3.0 to 5.5 V Block Diagram CLK1 FBIN CLKIN PLL CLK2 CLK3 CLK4 www.DataSheet4U.com MDS 574 B 1 Revision 051801 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com www.DataSheet4U.com ICS574 Zero Delay, Low Skew Buffer Pin Assignment CLKIN CLK1 CLK2 GND 1 2 3 4 8 7 6 5 FBIN CLK4 CLK3 VDD Standard 8 pin SOIC Pin Descriptions Number 1 2, 3, 6, 7 5 4 8 Name CLKIN CLK1:4 VDD GND FBIN Type I O P P I Description Clock input. Connect to input clock source. Four clock outputs. Power supply. Connect both pins to same voltage (either 3.3V or 5V). Connect to ground. Feedback input. Key: I = Input; O = output; P = power supply connection. External Components The ICS574 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1µF should be connected between VDD and GND on pins 4 and 5, as close to the device as possible. A series termination resistor of 33 Ω may be used close to the pin for each clock output to reduce reflections. www.DataSheet4U.com MDS 574 B 2 Revision 051801 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com www.DataSheet4U.com ICS574 Zero Delay, Low Skew Buffer Electrical Specifications Parameter Conditions Minimum ABSOLUTE MAXIMUM RATINGS (note 1) Supply voltage, VDD Referenced to GND -0.5 Inputs and Clock Outputs Referenced to GND -0.5 Electrostatic Discharge MIL-STD-883 2000 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Junction temperature Storage temperature -65 DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise) Operating Voltage, VDD 3.00 Input High Voltage, VIH VDD/2+1 Input Low Voltage, VIL Output High Voltage, VOH IOH=-18 mA 2.4 Output Low Voltage, VOL IOL=18 .


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