DatasheetsPDF.com

P-80C52 Dataheets PDF



Part Number P-80C52
Manufacturers Temic
Logo Temic
Description (P-80C32 / P-80C52) CMOS 8-Bit Microcontroller
Datasheet P-80C52 DatasheetP-80C52 Datasheet (PDF)

www.DataSheet4U.com 80C32/80C52 CMOS 0 to 44 MHz Single Chip 8–bit Microcontroller 1. Description TEMIC’s 80C52 and 80C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit Microcontroller. The fully static design of the TEMIC 80C52/80C32 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C52 retains all the features of the 8052: 8 K bytes of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit .

  P-80C52   P-80C52


Document
www.DataSheet4U.com 80C32/80C52 CMOS 0 to 44 MHz Single Chip 8–bit Microcontroller 1. Description TEMIC’s 80C52 and 80C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit Microcontroller. The fully static design of the TEMIC 80C52/80C32 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C52 retains all the features of the 8052: 8 K bytes of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit timers; a 6-source, 2-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuits. In addition, the 80C52 has 2 D 80C32: Romless version of the 80C52 D 80C32/80C52-L16: Low power version VCC: 2.7 – 5.5 V Freq: 0-16 MHz D 80C32/80C52-12: 0 to 12 MHz D 80C32/80C52-16: 0 to 16 MHz D 80C32/80C52-20: 0 to 20 MHz D 80C32/80C52-25: 0 to 25 MHz D 80C32/80C52-30: 0 to 30 MHz D 80C32/80C52-36: 0 to 36 MHz software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the RAM, the timers, the serial port and the interrupt system continue to function. In the power down mode the RAM is saved and all other functions are inoperative. The 80C32 is identical to the 80C52 except that it has no on-chip ROM. TEMIC’s 80C52/80C32 are manufactured using SCMOS process which allows them to run from 0 up to 44 MHz with VCC = 5 V. TEMIC’s 80C52 and 80C32 are also available at 16 MHz with 2.7 V < VCC < 5.5 V. D 80C32-40: 0 to 40 MHz(1) D 80C32-42: 0 to 42 MHz(1) D 80C32-44: 0 to 44 MHz(1) Notes: 1. 0 to 70_C temperature range. 2. For other speed and temperature range availability, please contact your sales office. 2. Features D D D D D D D Power control modes 256 bytes of RAM 8 Kbytes of ROM (80C52) 32 programmable I/O lines Three 16 bit timer/counters 64 K program memory space 64 K data memory space D D D D D D Fully static design 0.8µ CMOS process Boolean processor 6 interrupt sources Programmable serial port Temperature range: commercial, industrial, automotive, military 3. Optional www.DataSheet4U.com D Secret ROM: Encryption D Secret TAG: Identification number Rev. I – September 18, 1998 1 www.DataSheet4U.com 80C32/80C52 4. Interface VCC VSS INT0 INT1 RST XTAL1 XTAL2 EA ALE PSEN WR RD AD0–AD7 A8–A15 Parallel I/O Ports & External Bus 8–BIT INTERNAL BUS Oscillator & Timing CPU RAM 256 bytes ROM 8 Kbytes Interrupt Unit Serial I/O Port Timer 0 Timer 1 Timer 2 P0 P1 P2 P3 RxD TxD T0 T1 T2 T2EX Figure 1. Block Diagram www.DataSheet4U.com 2 Rev. I – September 18, 1998 www.DataSheet4U.com 80C32/80C52 P1.1/T2EX P0.0/A0 P0.1/A1 P0.2/A2 6 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA NC ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 P2.2/A10 P2.3/A11 P2.1/A9 P2.4/A12 XTAL2 XTAL1 VSS NC WR/P3.6 RD/P3.7 P2.0/A8 80C32/80C52 DIL P1.1/T2EX P1.0/T2 A0/P0.0 A1/P0.1 A2/P0.2 A3/P0.3 P1.4 P1.3 P1.2 NC VCC LCC P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA 80C32/80C52 NC ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 XTAL2 XTAL1 NC P2.2/A10 P2.3/A11 WR/P3.6 VSS P2.0/A8 P2.1/A9 QFP Diagrams are for reference only. Package sizes are not to scale. Figure 2. Pin Configuration www.DataSheet4U.com P2.4/A12 RD/P3.7 P0.3/A3 P1.0/T2 VCC P1.4 P1.3 P1.2 NC Rev. I – September 18, 1998 3 www.DataSheet4U.com 80C32/80C52 5. Pin Description 5.1. VSS Circuit ground potential. 5.2. VCC Supply voltage during normal, Idle, and Power Down operation. 5.3. Port 0 Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1’s. Port 0 also outputs the code bytes during program verification in the 80C52. External pullups are required during program verification. Port 0 can sink eight LS TTL inputs. 5.4. Port 1 Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 1 also receives the low-order address byte during program verification. In the 80C52, Port 1 can sink/ source three LS TTL inputs. It can drive CMOS inputs without external pullups. 2 inputs of PORT 1 are also used for timer/counter 2 : P1.0 [T2]: External clock input for timer/counter 2. P1.1 [T2EX]: A trigger input for timer/counter 2, to be reloaded or captured causing the .


P-80C32 P-80C52 2SD1293M


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)