PIO

( DataSheet : www.DataSheet4U.com ) Features Compatible with an Embedded 32-bit ARM7TDMI™ Processor Up to 32 Programmable I/O Lines Interrupt Generation on Event Glitch Filter Fully Scan Testable (up to 98% Fault Coverage) Can be Directly Connected to the Atmel Implementation of the AMBA™ Peripheral Bus (APB) of the ARM7TDMI Microcontroller Multi-driver (Open Drain) Option Certain Options “Parametrizable” on Request: Number of Programmable Lines Glitch Filter Option Multi-driver (Open Drain) Option Reset State of PIO Status and Glitch Filter Status Description The Parallel Input/Output 1 (PIO1) 32-bit embedded core peripheral features 32 fullyprogrammable input/output lines, each of which may be dedicated as general purpose I/O or be multiplexed with a signal generated by another embedded peripheral, in order to optimize the use of available package pins in the overall system-on-chip design. The PIO1 controller provides a bit-maskable event driven internal interrupt signal. The PIO1 and other analog and digital modular embedded peripherals, together with a choice of microprocessor and DSP cores, on-chip RAM, ROM, EEPROM and Flash memory, as well as special purpose analog or digital user-developed blocks, allow rapid and cost-effective design and implementation of an optimized system-on-chip. The large range of functional blocks offers a realistic and efficient design pathway to system-level integration (SLI). The PIO1 is bus-compatible with the ARM7T...