P8M646YLG

P8M646YLG, P16M6412YLG SDRAM MODULE Features: PC-100 and PC133 Compatible JEDEC – Standard 168-pin , dual in-line memory Module (DIMM) TSOP components. Single 3.3v +.3v power supply. Nonbuffered fully synchronous; all signals measured on positive edge of system clock. Internal pipelined operation; column address can be changed every clock cycle. Quad internal banks for hiding row access/precharge. 64ms 4096 cycle refresh. All inputs, outputs, clocks LVTTL compatible. 8M, 16M x 64 DIMM PIN ASSIGNMENT (Front View) 168-Pin DIMM PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL Options: 6 - 8Mx12 SDRAM TSOP 12 - 8Mx12 SDRAM TSOP Part Number: P8M646YLG-XX P16M6412YLG-XX KEY DIMM MODULE TIMING PARAMETERS Module Component Clock CAS Marking Marking Frequency Latency -100CL3 -8A 100MHz 3 -133CL3 -75A 133MHz 3 GENERAL DESCRIPTION The P8M646YLG, P16M6412YLG, are high performance dynamic random-access 64MB and 128MB modules respectively. These modules are organized in a x64 configuration, and utilize quad bank architecture with a synchronous interface. All signals are registered on the positive edge of the clock signals CK0 through CK3. Read and write accesses to the SDRAM are burst oriented; accesses start at a location and continue for a programmed number of locations in a sequence. Accesses begin with an ACTIVE command, which is followed by a READ or WRITE command. _______________________________________________ _ ABSOLUTE MAXIMUM RATINGS: Voltage on Vcc Supp...