HY27UF161G2M

( DataSheet : www.DataSheet4U.com ) Preliminary HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Document Title 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 1) Initial Draft. 1) Correct Fig.10 Sequential out cycle after read 2) Add the text to Fig.1, Table.1, Table.2 - text : IO15 - IO8 (x16 only) 3) Delete ‘3.2 Page program NOTE 1. - Note : if possible it is better to remove this constrain 4) Change the text ( page 10,13, 45) - 2.2 Address Input : 28 Addresses -> 27 Addresses - 3.7 Reset : Fig.29 -> Fig.30 - 5.1 Automatic page read after power up : Fig.30 -> Fig.29 5) Add 5.3 Addressing for program operation & Fig.34 1) Change TSOP, WSOP, FBGA package dimension & figures. - Change TSOP, WSOP, FBGA package mechanical data - Change FBGA thickness (1.2 -> 1.0 mm) 2) Correct TSOP, WSOP Pin configurations. - 38th NC pin has been changed Lockpre(figure 3,4) 3) Edit figure 15,19 & table 4 4) Add Bad Block Management 5) Change Device Identifier 3rd Byte - 3rd Byte ID is changed. (reserved -> don't care) - 3rd Byte ID table is deleted. 1) Add Errata tCLS Specification Relaxed value 0 5 tCLH 10 15 tWP 25 40 tALS 0 5 tALH 10 15 tDS 20 25 tWC 50 60 tR 25 27 History Draft Date Aug. 2004 Remark Preliminary 0.1 Sep. 2004 Preliminary 0.2 Oct. 2004 Preliminary 0.3 0.4 2) LOCKPRE is changed to PRE. - Texts, Table, Figures are changed. 3) Add Note.4 (table.14) 4) Block Lock Mechanism is deleted. - Text...