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MB84VD2108x Dataheets PDF



Part Number MB84VD2108x
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description (MB84VD2108x / MB84VD2109x) 16M (x8/x16) FLASH MEMORY & 2M (x8/x16) STATIC RAM
Datasheet MB84VD2108x DatasheetMB84VD2108x Datasheet (PDF)

( DataSheet : www.DataSheet4U.com ) FUJITSU SEMICONDUCTOR DATA SHEET DS05-50201-3E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 16M (×8/×16) FLASH MEMORY & 2M (×8/×16) STATIC RAM MB84VD2108X-85/MB84VD2109X-85 s FEATURES • Power supply voltage of 2.7 V to 3.6 V • High performance 85 ns maximum access time • Operating Temperature −25 °C to +85 °C • Package 61-ball FBGA, 56-pin TSOP(I) (Continued) s PRODUCT LINE UP Flash Memory Ordering Part No. VCCf*, VCCs* = 3.0 V −0.3 V +0.6 V.

  MB84VD2108x   MB84VD2108x



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( DataSheet : www.DataSheet4U.com ) FUJITSU SEMICONDUCTOR DATA SHEET DS05-50201-3E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 16M (×8/×16) FLASH MEMORY & 2M (×8/×16) STATIC RAM MB84VD2108X-85/MB84VD2109X-85 s FEATURES • Power supply voltage of 2.7 V to 3.6 V • High performance 85 ns maximum access time • Operating Temperature −25 °C to +85 °C • Package 61-ball FBGA, 56-pin TSOP(I) (Continued) s PRODUCT LINE UP Flash Memory Ordering Part No. VCCf*, VCCs* = 3.0 V −0.3 V +0.6 V SRAM MB84VD2108X-85/MB84VD2109X-85 85 85 35 85 85 45 Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) *: Both VCCf and VCCs must be in recommended operation range when either part is being accessed. s PACKAGES 61-ball plastic FBGA 56-pin plastic TSOP(I) (BGA-61P-M02) (FPT-56P-M04) www.DataSheet4U.com www.DataSheet4U.com MB84VD2108X-85/MB84VD2109X-85 (Continued) 1. FLASH MEMORY • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations. Read-while-erase Read-while-program • Minimum 100,000 write/erase cycles • Sector erase architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VD2108X : Top sector MB84VD2109X : Bottom sector • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCCf write inhibit ≤ 2.5 V • Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2108X : SA37, SA38 MB84VD2109X : SA0, SA1) At VIH, allows removal of boot sector protection At VACC, program time will reduce by 40%. • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device. • Please refer to “MBM29DL16XTD/BD” data sheet in detailed function 2. SRAM • Power dissipation Operating: 50 mA Max. Standby: 7 µA Max. • Power down features using CE1s and CE2s • Data retention supply voltage : 1.5 V to 3.6 V • CE1s and CE2s Chip Select • Byte data control : LBs (DQ0 to DQ7) , UBs (DQ8 to DQ15) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MB84VD2108X-85/MB84VD2109X-85 s PIN ASSIGNMENTS (Top View) D10 N.C. B9 A15 A8 A11 A7 A8 A6 WE A5 B8 A12 B7 A19 B6 CE2s B5 C9 N.C. C8 A13 C7 A9 C6 N.C. C5 D9 N.C. D8 A14 D7 A10 E10 N.C. E9 A16 E8 SA E7 DQ6 F9 CIOf F8 DQ15/A-1 F7 DQ13 F6 DQ4 F5 DQ3 G9 VSS G8 DQ7 G7 DQ12 G6 VCCs G5 VCCf G4 DQ10 G3 DQ0 G2 CE1s H8 DQ14 H7 DQ5 H6 CIOs H5 DQ11 H4 DQ2 H3 DQ8 WP/ACC RESET RY/BY A4 LBS A3 A7 B4 UBS B3 A6 B2 A3 A1 N.C. C4 A18 C3 A5 C2 A2 D4 A17 D3 A4 D2 A1 D1 N.C. E4 DQ1 E3 VSS E2 A0 E1 N.C. F4 DQ9 F3 OE F2 CEf 61-ball FBGA (Continued) 3 MB84VD2108X-85/MB84VD2109X-85 (Continued) (Top View) N.C. A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE CE2s RESET WP/ACC RY/BY UBs LBs A18 A17 A7 A6 A5 A4 A3 A2 A1 N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A16 CIOf VSS SA DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 CIOs VCCs VCCf DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE1s CEf A0 56-pin TSOP (I) 4 MB84VD2108X-85/MB84VD2109X-85 s PIN DESCRIPTION Pin no. A0 to A16 A–1, A17 to A19 SA DQ0 to DQ15 CEf CE1s CE2s OE WE RY/BY UBs LBs CIOf CIOs RESET WP/ACC N.C. VSS VCCf VCCs Input/Output I I I I/O I I I I I O I I I I I I  Power Power Power Address Inputs (Common) Address Input (Flash) Address Input (SRAM) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Open Drain Output Upper Byte Control (SRAM) Lower Byte Control (SRAM) I/O Configuration (Flash) CIOf = VCCf is Word mode (×16) , CIOf = VSS is Byte mode (×8) I/O Configuration (SRAM) CIOs = VCCs is Word mode (×16) , CIOs = VSS is Byte mode (×8) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect/Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM) Function 5 MB84VD2108X-85/MB84VD2109X-85 s BLOCK DIAGRAM VCCf A0 to A19 A0 to A19 A−1 WP/ACC RESET CEf CIOf VSS RY/BY 16.


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