Document
TC58V64ADC
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64-MBIT (8M × 8 BITS) CMOS NAND E PROM (8M BYTE SmartMedia DESCRIPTION
2
TM
)
The TC58V64A is a single 3.3-V 64-Mbit (69,206,016) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 16 pages × 1024 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (8 Kbytes + 512 bytes: 528 bytes × 16 pages). The TC58V64A is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. The data stored in the TC58V64ADC needs to comply with the data format standardized by the SSFDC Forum in order to maintain compatibility with other SmartMediaTM systems.
FEATURES
• Organization Memory cell array 528 × 16K × 8 Register 528 × 8 Page size 528 bytes Block size (8K + 512) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read Mode control Serial input/output, Command control Complies with the SmartMediaTM Electrical Specification and Data Format Specification issued by the SSFDC Forum • • • Power supply VCC = 3.3 V ± 0.3 V Access time Cell array-register 25 µs max Serial Read cycle 50 ns min Operating current Read (50-ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 100 µA max Package TC58V64ADC: FDC-22A (Weight: 1.8 g typ.)
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PIN ASSIGNMENT (TOP VIEW)
VSS CLE ALE
PIN NAMES
I/O4 VSS VSS
WE
WP
I/O1 I/O2
I/O3
I/O1~I/O8
CE
I/O port Chip enable Write enable Read enable Command latch enable Address latch enable Write protect Ready/Busy Ground Input Low Voltage Detect Power supply Ground
TM
WE RE CLE ALE WP
1 2 3 4 5 6 7 8 9 10 11
RY/BY GND LVD
22 21 20 19 18 17 16 15 14 13 12
VCC VSS
VCC
CE
RE
RY/BY GND LVD I/O8 I/O7 I/O6 I/O5 VCC
is a trademark of Toshiba Corporation.
000707EBA2
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk.
2000-08-27
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TC58V64ADC
BLOCK DIAGRAM
VCC VSS Status register
I/O1 I/O control circuit ~ I/O8
CE
Address register
Column buffer Column decoder
Command register
Data register Sense amp ROW address decoder ROW address buffer decoder
CLE ALE Logic control WE RE WP RY/BY RY/BY HV generator Control circuit
Memory cell array
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VIN VI/O PD Tstg Topr PARAMETER Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Storage Temperature Operating Temperature RATING −0.6~4.6 −0.6~4.6 −0.6 V~VCC + 0.3 V (≤ 4.6 V) 0.3 −20~65 0~55 UNIT V V V W °C °C
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMBOL CIN COUT Input Output PARAMETER CONDITION VIN = 0 V VOUT = 0 V MIN MAX 10 10 UNIT pF pF
* This parameter is periodically sampled and is not tested for every device.
000707EBA2
• The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is p.