SDP60N03L

S DP /B 60N03L S amHop Microelectronics C orp. May,2004 ver1.1 N-Channel Logic Level E nhancement Mode Field E ffect Transistor 4 P R ODUC T S UMMAR Y V DS S 30V F E AT UR E S S uper high dense cell design for extremely low R DS (ON). High power and current handling capability. TO-220 & TO-263 package. ID 56A R DS (on) ( m W ) Max 11 @ V G S = 10V 19 @ V G S = 4.5V D D G D S G S G S DP S E R IE S TO-220 S DB S E R IE S TO-263(DD-P AK) S ABS OLUTE MAXIMUM R ATINGS (TC =25 C unless otherwise noted) P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous -P ulsed a S ymbol V DS V GS @ TJ=125 C ID IDM IS PD T J , T S TG Limit 30 20 56 168 60 75 -65 to 175 Unit V V A A A W C Drain-S ource Diode Forward C urrent Maximum P ower Dissipation @ Tc=25 C Operating and S torage Temperature R ange THE R MAL C HAR AC TE R IS TIC S Thermal R esistance, Junction-to-C ase Thermal R esistance, Junction-to-Ambient www.DataSheet4U.com 1 R JC R JA www.DataSheet4U.com 2.5 C /W C /W 62.5 S DP /B 60N03L E LE CTR ICAL CHAR ACTE R IS TICS (T C =25 C unless otherwise noted) 4 Parameter OFF CHAR ACTE R IS TICS Drain-S ource Breakdown Voltage Zero Gate Voltage Drain Current Gate-Body Leakage S ymbol BV DS S IDS S IGS S V GS (th) R DS (ON) ID(ON) gFS C IS S C OS S CRSS b Condition V GS = 0V, ID = 250uA V DS = 24V, V GS =0V V GS = 16V, V DS = 0V V DS = V GS , ID = 250uA V GS = 10V, ID = 30A V GS = 4.5V, ID = 24A V GS = 10V, V DS = 10V V DS = 10V, ID = 26A M...