DatasheetsPDF.com

TSI106G-xxx Dataheets PDF



Part Number TSI106G-xxx
Manufacturers Tundra Semiconductor
Logo Tundra Semiconductor
Description PowerPC Host Bridge
Datasheet TSI106G-xxx DatasheetTSI106G-xxx Datasheet (PDF)

Tsi106™ Feature Sheet PowerPC™ Host Bridge Features Processor Interface • Supports the following Motorola processors: MPC603e, MPC740, MPC745, MPC750, MPC755, MPC7400, and MPC7410 • Supports the following IBM processors: PowerPC 603e, PowerPC 740, and PowerPC 750 • Processor bus frequency up to 83 MHz • 64-bit data bus and 32-bit address bus • Supports either an external L2 cache or a secondary processor • Full memory coherency supported The Tsi106 Advantage The Tundra Semiconductor Corporation.

  TSI106G-xxx   TSI106G-xxx



Document
Tsi106™ Feature Sheet PowerPC™ Host Bridge Features Processor Interface • Supports the following Motorola processors: MPC603e, MPC740, MPC745, MPC750, MPC755, MPC7400, and MPC7410 • Supports the following IBM processors: PowerPC 603e, PowerPC 740, and PowerPC 750 • Processor bus frequency up to 83 MHz • 64-bit data bus and 32-bit address bus • Supports either an external L2 cache or a secondary processor • Full memory coherency supported The Tsi106 Advantage The Tundra Semiconductor Corporation (Tundra) Tsi106 PowerPC Host Bridge provides proven system interconnect between PowerPC host processors and the PCI bus. PCI support allows system designers to develop systems quickly using peripherals already designed for PCI and the other standard interfaces available in the personal computer industry. The Tsi106 integrates secondary cache control and a high-performance memory controller that supports DRAM, SDRAM, ROM, and Flash ROM. The Tsi106 uses an advanced, 3.3-volt CMOS process technology and is fully compatible with TTL devices. Figure 1: Tsi106 Block Diagram 64-bit Data/32-bit Address 66-83 MHz Bus Up to 1-Mbyte of SRAM Memory Interface • Supports DRAM (page mode, EDO), and SDRAM • 64-bit data bus that operates up to 66 MHz • Supports 1 to 8 banks built of x1, x4, x8, x9, x16 or x18 DRAM chips • 1 Gbyte of RAM space, 16 Mbytes of ROM space • Supports writing to Flash EPROMs • Supports parity or error-correcting code (ECC) Processor Interface L2 Cache Interface Memory Interface Power Management Configuration Registers Error/Interrupt Control 66 MHz, 64-bit Bus DRAM, SDRAM, ROM, Flash PCI Interface • Compliant with PCI Specification, (Revision 2.1) • Supports up to 33 MHz operation • Read and write buffers to improve PCI performance • Supports concurrent transactions on processor and PCI buses • 3.3V/5V compatible IEEE1149.1 Boundary Scan JTAG PCI Interface 80C1000_BK001_01 32-bit Address and Data 25-33 MHz PCI Bus (Rev. 2.1) Multiprocessor and L2 Cache Support The Tsi106 supports a programmable interface to microprocessors operating at bus frequencies up to 83 MHz. The Tsi106 Processor interface allows for a variety of system configurations by providing support for either a second processor or a secondary L2 cache. The L2 cache control unit generates the arbitration and support signals necessary to maintain a write-through or write-back lookaside cache. Package • 304-pin, ceramic ball grid array (CBGA) • Package outline 21 mm x 25 mm, 1.27 pitch www.DataSheet4U.com www.DataSheet4U.com © 2003 Tundra Semiconductor Corporation. All Rights Reserved. -1- Document: 80C1000_FB001_02 Tsi106: PowerPC Host Bridge Features (continued) Secondary Cache Control • 256-Kbyte, 512-Kbyte, 1-Mbyte sizes • Direct-mapped • Provides support for either asynchronous SRAM, burst SRAM, or pipelined burst SRAM • Supports external lookaside L2 cache controller Integrated Memory Controller The Tsi106 Memory interface controls processor and PCI interactions.



Similar Datasheet



TSI-10N << | TSI106G-xxx | >> HY62256ALP


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)