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8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH ZBT SRAM
8Mb ZBT® SRAM
FEATURES
• • • • • • • • • • • • • • • • • • • • High frequency and 100 percent bus utilization Fast cycle times: 10ns, 11ns and 12ns Single +3.3V ±5% power supply (VDD) Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) Advanced control logic for minimum control signal interface Individual BYTE WRITE controls may be tied LOW Single R/W# (read/write) control pin CKE# pin to enable clock and suspend operations Three chip enables for simple depth expansion Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed, fully coherent WRITE Internally self-timed, registered outputs to eliminate the need to control OE# SNOOZE MODE for reduced-power standby Common data inputs and data outputs Linear or Interleaved Burst Modes Burst feature (optional) Pin/function compatibility with 2Mb, 4Mb, and 18Mb ZBT SRAM 100-pin TQFP 165-pin FBGA Automatic power-down
MT55L512L18F, MT55L512V18F, MT55L256L32F, MT55L256V32F, MT55L256L36F, MT55L256V36F
3.3V VDD, 3.3V or 2.5V I/O
100-Pin TQFP1
165-Pin FBGA
OPTIONS
• Timing (Access/Cycle/MHz) 7.5ns/10ns/100 MHz 8.5ns/11ns/90 MHz 9ns/12ns/83 MHz • Configurations 3.3V I/O 512K x 18 256K x 32 256K x 36 2.5V I/O 512K x 18 256K x 32 256K x 36 • Package 100-pin TQFP 165-pin FBGA • Operating Temperature Range Commercial (0ºC to +70ºC) Industrial (-40°C to +85°C)**
Part Number Example:
MARKING
-10 -11 -12
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
* A Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/support/index.html. ** Industrial temperature range offered in specific speed grades and configurations. Contact factory for more information.
MT55L512L18F MT55L256L32F MT55L256L36F MT55L512V18F MT55L256V32F MT55L256V36F T F* None IT
GENERAL DESCRIPTION
The Micron® Zero Bus Turnaround™ (ZBT®) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. Micron’s 8Mb ZBT SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization, eliminating any turnaround cycles for READ to WRITE, or WRITE to READ, transitions. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), cycle start input
MT55L256L32FT-11
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM MT55L512L18F_C.p65 – Rev. 2/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc.
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8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM 512K x 18
19 SA0, SA1, SA MODE CLK CKE# K CE ADV/LD# K WRITE ADDRESS REGISTER ADDRESS REGISTER 19 SA1 D1 SA0 D0 17 Q1 SA1' SA0' Q0 19 19 O U T P U T B U F F E R S E 19
BURST LOGIC
ADV/LD# BWa# BWb# R/W# WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
18
512K x 9 x 2 WRITE DRIVERS
18
MEMORY ARRAY
18
S E N S E A M P S
D A T A
18
S T E E R I N G
18
18
DQs
18
OE# CE# CE2 CE2#
READ LOGIC
INPUT E REGISTER
FUNCTIONAL BLOCK DIAGRAM 256K x 32/36
18 SA0, SA1, SA MODE CLK CKE# K CE ADV/LD# K WRITE ADDRESS REGISTER ADDRESS REGISTER 18 SA1 D1 SA0 D0 16 Q1 SA1' SA0' Q0 18 18 O U T P U T B U F F E R S E 18
BURST LOGIC
ADV/LD# BWa# BWb# BWc# BWd# R/W# WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
36
256K x 8 x 4 (x32) WRITE DRIVERS
36
256K x 9 x 4 36 (x36) MEMORY ARRAY
S E N S E A M P S
D A T A
36
S T E E R I N G
36
36
DQs DQPa DQPb DQPc DQPd
36
OE# CE# CE2 CE2#
INPUT E REGISTER
READ LOGIC
NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams for detailed information.
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM MT55L512L18F_C.p65 – Rev. 2/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH ZBT SRAM
GENERAL DESCRIPTION (continued)
(ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc#, and BWd#), and read/write (R/W#). Asynchronous inputs include the output enable (OE#, which may be tied LOW for control signal minimization), clock (CLK), and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW, or left unconnected if burst is unused. The flow-through dataout (Q) is enabled by OE#. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. All READ, WRITE, and DESELECT cycles are initiated by the ADV/LD# input. Subsequent burst addresses can be internally generated as controlle.