Document
W134M/W134S
Direct Rambus™ Clock Generator
Features
• Differential clock source for Direct Rambus™ memory subsystem for up to 800-MHz data transfer rate • Provide synchronization flexibility: the Rambus® Channel can optionally be synchronous to an external system or processor clock • Power-managed output allows Rambus Channel clock to be turned off to minimize power consumption for mobile applications • Works with Cypress CY2210, W133, W158, W159, W161, and W167 to support Intel® architecture platforms • Low-power CMOS design packaged in a 24-pin QSOP (150-mil SSOP) package
Description
The Cypress W134M/W134S provides the differential clock signals for a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an external system clock but can also be used in systems that do not require synchronization of the Rambus clock.
Block Diagram
REFCLK MULT0:1
Pin Configuration
PLL
PCLKM SYNCLKN
Phase Alignment
Output Logic
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S0:1 STOPB
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CLK CLKB
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VDDIR
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VDD GND GND GND VDD
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S0 S1
24 23 22 21 20 19 18 17 16 15 14 13
REFCLK
VDD GND CLK NC CLKB GND VDD MULT0 MULT1 GND
PCLKM SYNCLKN
VDDIPD STOPB PWRDNB
Test Logic
Cypress Semiconductor Corporation Document #: 38-07426 Rev. *C
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3901 North First Street
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San Jose CA 95134 • 408-943-2600 Revised June 1, 2005
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W134M/W134S
Pin Definitions
Pin Name REFCLK PCLKM No. 2 6 Type I I Description Reference Clock Input. Reference clock input, normally supplied by a system frequency synthesizer (Cypress W133). Phase Detector Input. The phase difference between this signal and SYNCLKN is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio Logic is not used, this pin would be connected to Ground. Phase Detector Input. The phase difference between this signal and PCLKM is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio Logic is not used, this pin would be connected to Ground. Clock Output Enable. When this input is driven to active LOW, it disables the differential Rambus Channel clocks. Active LOW Power-down. When this input is driven to active LOW, it disables the differential Rambus Channel clocks and places the W134M/W134S in power-down mode. PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to determine the multiply ratio for the PLL for the input REFCLK.
MULT0 0 0 1 1 MULT1 0 1 1 0 W134M PLL/REFCLK 4.5 6 8 5.333 W134S PLL/REFCLK 4 6 8 5.333
SYNCLKN
7
I
STOPB PWRDNB MULT 0:1
11 12 15, 14
I I I
CLK, CLKB S0, S1
20, 18 24, 23
O I
Complementary Output Clock. Differential Rambus Channel clock outputs. Mode Control Input. These inputs control the operating mode of the W134M/W134S.
S0 0 0 1 1 S1 0 1 0 1 MODE Normal Output Enable Test Bypass Test
NC VDDIR VDDIPD VDD GND
19 1 10 3, 9, 16, 22 4, 5, 8, 13, 17, 21
–
No Connect
RefV Reference for REFCLK. Voltage reference for input reference clock. RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB. P G Power Connection. Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection. Connect all ground pins to the common system ground plane.
W133 W158 W159 W161 W167 CY2210
W134M/W134S
Refclk
PLL
Phase Align D
Busclk
Pclk/M
RMC
RAC
Synclk/N
M
Pclk
N Synclk
4
DLL
Gear Ratio Logic
Figure 1. DDLL System Architecture
Document #: 38-07426 Rev. *C
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W134M/W134S
Key Specifications
Supply Voltage: ...................................... VDD = 3.3V±0.165V Operating Temperature: ................................... 0°C to +70°C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage: ........................................ VDD+0.5V Maximum Input Frequency: .....................................100 MHz Output Duty Cycle:...................................40/60% worst case Output Type: ...........................Rambus signaling level (RSL) (Rambus Channel). At the mid-point of the channel, the RAC senses Busclk using its own DLL for clock alignment, followed by a fixed divide-by-4 that generates Synclk. Pclk is the clock used in the memory controller (RMC) in the core logic, and Synclk is the clock used at the core logic interface of the RAC. The DDLL together with the Gear Ratio Logic enables users to exchange data directly from the Pclk domain to the Synclk domain without incurring additional latency for synchronization. In general, Pclk and Synclk can be of different frequencies, so the Gear Ratio Logic must select the appropriate M and N dividers such that the frequencies of Pclk/M and Synclk/N are equal. In one interesting example, Pclk = 133 MHz, Synclk = 10.