W134S

W134M/W134S Direct Rambus™ Clock Generator Features Differential clock source for Direct Rambus™ memory subsystem for up to 800-MHz data transfer rate Provide synchronization flexibility: the Rambus® Channel can optionally be synchronous to an external system or processor clock Power-managed output allows Rambus Channel clock to be turned off to minimize power consumption for mobile applications Works with Cypress CY2210, W133, W158, W159, W161, and W167 to support Intel® architecture platforms Low-power CMOS design packaged in a 24-pin QSOP (150-mil SSOP) package Description The Cypress W134M/W134S provides the differential clock signals for a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an external system clock but can also be used in systems that do not require synchronization of the Rambus clock. Block Diagram REFCLK MULT0:1 Pin Configuration PLL PCLKM SYNCLKN Phase Alignment Output Logic w S0:1 STOPB w w .D t a S a CLK CLKB e h VDDIR t e VDD GND GND GND VDD U 4 1 2 3 4 5 6 7 8 9 10 11 12 .c m o S0 S1 24 23 22 21 20 19 18 17 16 15 14 13 REFCLK VDD GND CLK NC CLKB GND VDD MULT0 MULT1 GND PCLKM SYNCLKN VDDIPD STOPB PWRDNB Test Logic Cypress Semiconductor Corporation Document #: 38-07426 Rev. *C 3901 North First Street San Jose CA 95134 408-943-2600 Revised June 1, 2005 w w , w .D at h S a t e e 4U . m o c W134M/W134S Pin Definitions Pin Name REFCLK PCLKM No. 2 ...