(CY7C006A - CY7C017A) Dual Port Static RAM
CY7C006A CY7C007A CY7C017A32K/16K x 8, 32K x 9 Dual-Port Static RAM
Features
• True dual-ported memory cells which all...
Description
CY7C006A CY7C007A CY7C017A32K/16K x 8, 32K x 9 Dual-Port Static RAM
Features
True dual-ported memory cells which allow simultaneous access of the same memory location 16K x 8 organization (CY7C006A)
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32K x 8 organization (CY7C007A) 16K x 9 organization (CY7C016A) 32K x 9 organization (CY7C017A) 0.35-micron CMOS for optimum speed/power High-speed access: 12[1]/15/20 ns Low operating power — Active: ICC = 180 mA (typical) — Standby: ISB3 = 0.05 mA (typical) Fully asynchronous operation
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CY7C006A/CY7C007A CY7C016A/CY7C017A
32K/16K x8, 32K/16K x9 Dual-Port Static RAM
Automatic power-down Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flags for port-to-port communication Pin select for Master or Slave Commercial temperature range
Available in 68-pin PLCC (CY7C006A, CY7C007A and CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A)
Logic Block Diagram
R/WL CEL OEL
I/O0L–I/O7/8L
[2]
8/9
[4] A0L–A13/14L
14/15
[4] A0L–A13/14L CEL OEL R/WL SEML
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Address Decode
14/15
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I/O Control
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U 4
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m o
R/WR CER OER
8/9
[2]
I/O Control
I/O0R–I/O7/8R
True Dual-Ported RAM Array
Address Decode
14/15
14/15
A0R–A13/14R
[4]
Interrupt Semaphore Arbitration
BUSYL INTL
[3]
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