KU80960CF

w w w .D at Embedded Microprocessor S a Product Features s s s s . U 80960CF-40, -33, -25 4 t e High-Performance Superscalar 32-Bit e h Datasheet Socket and Object Code Compatible with 80960CA Two Instructions/Clock Sustained Execution Four 71 Mbytes/s DMA Channels with Data Chaining Demultiplexed 32-Bit Burst Bus with Pipelining s m o c s s s w s s w 32-Bit Parallel Architecture — Two Instructions/clock Execution — Load/Store Architecture — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers — Manipulates 64-Bit Bit Fields — 11 Addressing Modes — Full Parallel Fault Model — Supervisor Protection Model Fast Procedure Call/Return Model — Full Procedure Call in 4 Clocks On-Chip Register Cache — Caches Registers on Call/Ret — Minimum of 6 Frames Provided — Up to 15 Programmable Frames On-Chip Instruction Cache — 4 Kbyte Two-Way Set Associative — 128-Bit Path to Instruction Sequencer — Cache-Lock Modes — Cache-Off Mode High Bandwidth On-Chip Data RAM — 1 Kbyte On-Chip Data RAM — Sustains 128 bits per Clock Access Selectable Big or Little Endian Byte Ordering s w .D t a S a e h s s t e s Four On-Chip DMA Channels — 71 Mbytes/s Fly-by Transfers — 40 Mbytes/s Two-Cycle Transfers — Data Chaining — Data Packing/Unpacking — Programmable Priority Method 32-Bit Demultiplexed Burst Bus — 128-Bit Internal Data Paths to and from Registers — Burst Bus for DRAM Interfacing — Address Pipelining Option — Fully Programmable Wait States — Supports 8-, 16- or 32-...