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NT256D64S88B1GY Dataheets PDF



Part Number NT256D64S88B1GY
Manufacturers Nanya Technology
Logo Nanya Technology
Description (NT256D64S88Bxx) 256MB DDR DIMM
Datasheet NT256D64S88B1GY DatasheetNT256D64S88B1GY Datasheet (PDF)

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) 512MB, 256MB and 128MB PC3200, PC2700 and PC2100 Unbuffered DDR DIMM 184 pin Unbuffered DDR DIMM Based on DDR400/333/266 256M bit B Die device Features • 184 Dual In-Line Memory Module (DIMM) • Unbuffered DDR DIMM based on 256M bit die B device, organized as either 32Mbx8 or 16Mbx16 • Performance: PC3200 PC2700 PC2100 Speed Sort DIMM CAS .

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NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) 512MB, 256MB and 128MB PC3200, PC2700 and PC2100 Unbuffered DDR DIMM 184 pin Unbuffered DDR DIMM Based on DDR400/333/266 256M bit B Die device Features • 184 Dual In-Line Memory Module (DIMM) • Unbuffered DDR DIMM based on 256M bit die B device, organized as either 32Mbx8 or 16Mbx16 • Performance: PC3200 PC2700 PC2100 Speed Sort DIMM CAS Latency fCK tCK Clock Frequency Clock Cycle 5T 3 200 5 400 6K 2.5 166 6 333 75B 2.5 133 7.5 266 MHz ns MHz Unit • DRAM DLL aligns DQ and DQS transitions with clock transitions • Address and control signals are fully synchronous to positive clock edge • Programmable Operation: - DIMM CAS Latency: 2, 2.5, 3 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write • Auto Refresh (CBR) and Self Refresh Modes • Automatic and controlled precharge commands • 7.8 µs Max. Average Periodic Refresh Interval • Serial Presence Detect EEPROM • Gold contacts • SDRAMs are packaged in TSOP packages • “Green” packaging – lead free fDQ DQ Burst Frequency • Intended for 133, 166 and 200 MHz applications • Inputs and outputs are SSTL-2 compatible • VDD = VDDQ = 2.5V ± 0.2V (2.6V ± 0.1V for PC3200) • SDRAMs have 4 internal banks for concurrent operation • Differential clock inputs • Data is read or written on both clock edges Description NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G, NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology. NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8 TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G, NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices. NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules, organized as single rank using four 16Mx16 TSOP devices. Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC. REV 2.2 Aug 3, 2004 1 NANYA reserves the right to change products and specifications without notice. © NANYA TECHNOLOGY CORPORATION Preliminary NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Ordering Information Part Number NT512D72S8PB0G-5T Organization Speed Power Leads 64Mx72 NT512D64S8HB1G-5T 64Mx64 NT512D64S8HB1GY-5T (lead free) NT256D72S890G-5T PC3200 200MHz (5ns @ CL = 3) 32Mx72 DDR400 3-3-3 166MHz (6ns @ CL = 2.5) 2.6V NT256D64S88B1G-5T 32Mx64 NT256D64S88B1GY-5T (lead free) NT128D64SH4B1G-5T 16Mx64 NT512D64S8HB1G-6K 64Mx64 NT512D64S8HB1GY-6K (lead free) NT256D64S88B1GY-6K (lead free) 32Mx64 NT256D64S88B0G-6K 2.5V NT128D64SH4B1G-6K 16Mx64 PC2700 166MHz (6ns @ CL = 2.5) DDR333 2.5-3-3 133MHz (7.5ns @ CL = 2) Gold NT512D64S8HB0G-75B 64Mx64 PC2100 133MHz (7.5ns @ CL = 2.5) 32Mx64 DDR266B 2.5-3-3 100MHz (10ns @ CL = 2) NT256D64S88B0G-75B NT128D64SH4B1G-75B 16Mx64 For the closest sales office or information, please visit: www.nanya.com Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 REV 2.2 Aug 3, 2004 2 NANYA reserves the right to change products and specifications without notice. © NANYA TECHNOLOGY CORPORATION Preliminary NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Pin Description CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 RAS CAS WE S0, S1 A0-A9, A11, A12 A10/AP BA0, BA1 VREF VDDID Differential Clock Inputs. Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Auto-precharge SDRAM Bank Address Inputs Ref. Voltage for SSTL_2 inputs VDD Identification flag. DQ0-DQ63 DQS0-DQS7 DM0-DM7 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD Data input/output Bidirectional data strobes Input Data Mask Power Su.


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