Document
E2L1056-39-72 This version: Jul. 1999 MS82V16520 m Previous version: Sep. 1998 ¡ Semiconductor o c . MS82V16520 U 4 262,144-Word ¥ 32-Bit ¥t2-Bank Synchronous Graphics RAM e e h S DESCRIPTION a t a is a synchronous graphics random access memory organized as 256 K words ¥ 32 The MS82V16520 D bits ¥ 2 banks. . Thisw device can operate up to 143 MHz by using synchronous interface. In addition, it has 8-column Block Write function and Write per bit function which improves performance in graphics w wsystems. ¡ Semiconductor
FEATURES
• 262,144 words ¥ 32 bits ¥ 2 banks memory • Single 3.3 V ± 0.3 V power supply • LVTTL compatible inputs and outputs • All input signals are latched at rising edge of system clock • Auto precharge and controlled precharge • Internal pipelined operation: column address can be changed every clock cycle • Dual internal banks controlled by A10 (Bank Address: BA) • Independent byte operation via DQM0 to DQM3 • 8-column Block Write function • Persistent write per bit function • Programmable burst sequence (Sequential/Interleave) • Programmable burst length (1, 2, 4, 8 and full page) • Programmable CAS latency (2, 3) • Burst stop function (full-page burst) • Power Down operation and Clock Suspend operation • Auto refresh and self refresh capability • 2,048 refresh cycles/32 ms • Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (Product : MS82V16520-xGA) x indicates speed rank.
PRODUCT FAMILY
MS82V16520-7 MS82V16520-8
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Clock Frequency MHz (Max.) 143 125
Package
100-pin Plastic QFP (14 ¥ 20 mm)
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PIN CONFIGURATION (TOP VIEW)
84 DQ31 83 DQ30 100 DQ2 99 VSSQ 82 VSSQ 81 DQ29 98 DQ1 97 DQ0 96 VCC 95 NC 86 NC 85 VSS 94 NC 93 NC 92 NC 91 NC 90 NC 89 NC 88 NC 87 NC
DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ DQ16 DQ17 VSSQ DQ18 DQ19 VCCQ VCC VSS DQ20 DQ21 VSSQ DQ22 DQ23 VCCQ DQM0 DQM2 WE CAS RAS CS BA (A10) A8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36
MS82V16520
80 DQ28 79 VCCQ 78 DQ27 77 DQ26 76 VSSQ 75 DQ25 74 DQ24 73 VCCQ 72 DQ15 71 DQ14 70 VSSQ 69 DQ13 68 DQ12 67 VCCQ 66 VSS 65 VCC 64 DQ11 63 DQ10 62 VSSQ 61 DQ9 60 DQ8 59 VCCQ 58 NC 57 DQM3 56 DQM1 55 CLK 54 CKE 53 DSF 52 NC 51 A9 (AP)
37 38 39 40 41 42 43 44 45 46 47 48
A0 A1 A2 A3 VCC NC NC NC NC NC NC NC NC NC NC VSS A4 A5 A6 A7
100-Pin Plastic QFP
Pin Name A0 - A10 A0 - A9 A0 - A7 BA (A10) DQ0 - DQ31 CS RAS CAS WE
Function Address Inputs Row Address Inputs Column Address Inputs Bank Address Data Inputs/Outputs Chip Select Row Address Strobe Column Address Strobe Write Enable
49 50
Pin Name DQM0 - DQM3 DSF CKE CLK VCC VSS VCCQ VSSQ NC
Function DQ Mask Enable Special Function Enable Clock Enable System Clock Input Supply Voltage Ground Supply Voltage for DQ Ground for DQ No Connection
Note:
The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/66
¡ Semiconductor
MS82V16520
BLOCK DIAGRAM
Refresh Counter
Row Decoders
Timing Generator 8Mb Memory Cells Bank - A Sense Amplifiers Column Decoders
Row Decoders
CLK CKE CS RAS CAS WE DSF VCC/VCCQ VSS/VSSQ
Address Buffers
A0 A1 A2
32 I/O Buffers DQ0 to 31
A10
8Mb Memory Cells Bank - B Sense Amplifiers Column Decoders 32
32
DQM0 to 3 Color Register (32 bits) Mask Register (32 bits)
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¡ Semiconductor
MS82V16520
PIN DESCRIPTION
CLK CS CKE Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0, DQM1, DQM2 and DQM3. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 – RA9 Column address: CA0 – CA7 BA (A10) RAS CAS WE DSF DQM0 DQM3 DQi DSF is part of the inputs of graphics command of the MS82V16520. If DSF is inactive (Low level), MS82V16520 operates just like SDRAM. Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal. Data inputs/outputs are multiplexed on the same pin. 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0, DQM1, DQM2, and DQM3 are invalid. 2. When issuing an active, read or write command, the bank is selected by BA (A10). Functionality depends on the combination. For details, see the function truth table. Selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. BA = "L" : Bank A, BA = "H" : Bank B
*Notes:
BA (A10) 0 1
Active, read or write Bank A Bank B
3. The auto precharge func.