TOSHIBA
11:5516321-20/25/35
SILICON GATE CMOS
32,768 WORD x 16 BIT CMOS STATIC RAM
Description
The TC551632J is a 524,288 bit high speed CMOS static random access memory organized as 32,768 words by 16 bits and operated from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable hi~peed operation.
The TC551632J features low power dissipation when the device is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls.
The TC551632J is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and outputs are TIL compatible.
The TC551632J is available in a 400mil width, 40-pin SOJ suitable for high density surface assembly.
Features
• Fast access time - TC551632J-20 20ns (max.) - TC551632J-25 25ns (max.) - TC551632J-35 35ns (max.)
• Low power dissipation
Cycle Time
20
Operation (max.)
- Standby:
1mA (max.)
• Single 5V power supply: 5V±10%
• Fully static operation
• Inputs and outputs TIL compatible
• Output buffer control:
OE
• Data byte controls:
LB, UB
• Package:
SOJ40-P-400
Pin Names AO - A14
1/01 - 1/016 CE WE OE
LB, UB VDD GND
Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Data Byte Control Inputs Power (+5V) Ground
Pin Connection (Top View)
TC551632J
A3 A2 Al AO CE VOl 1/02 1103 1104
Voo
GND
1105 1/06 1/07 1108 WE A14 A13 A12 All
A4
AS ill UB LB
1/016
11015
1/014 1/013
GND
Voo
1/012 11011
1/010 1109
A6
A7 A8 A9 A10
(SOJ)
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
8·95
TC551632J-20/25/35 Block Diagram
Static RAM
MEMORY CELL ARRAY 256x 128x 16
(524,288)
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