EX256

v4.2 eX Family FPGAs FuseLock Leading Edge Performance 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out (Pad-to-Pad) Specifications 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros) 0.22µm CMOS Process Technology Up to 132 User-Programmable I/O Pins Features High-Performance, Low-Power Antifuse FPGA LP/Sleep Mode for Additional Power Savings Advanced Small-Footprint Packages Hot-Swap Compliant I/Os Single-Chip Solution Nonvolatile Live on Power-Up No Power-Up/Down Sequence Required for Supply Voltages Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power-Up Individual Output Slew Rate Control 2.5V, 3.3V, and 5.0V Mixed-Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength Software Design Support with Actel Designer and Libero™ Integrated Design Environment (IDE) Tools Up to 100% Resource Utilization with 100% Pin Locking Deterministic Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Fuselock™ Secure Programming Technology Prevents Reverse Engineering and Design Theft Product Profile Device Capacity System Gates Typical Gates Register Cells Dedicated Flip-Flops Maximum Flip-Flops Combinatorial Cells Maximum User I/Os Global Clocks Hardwired Routed Speed Grades Temperature Grades* Package (by pin count) TQFP CSP eX64 3...