MC74AC109

MC74AC109, MC74ACT109 Dual JK Positive Edge−Triggered Flip−Flop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Outputs Source/Sink 24 mA ′ACT109 Has TTL Compatible Inputs VCC CD2 J2 K2 CP2 SD2 Q2 Q2 16 15 14 13 12 11 10 9 CD J K CP SD Q Q CD1 J1 K1 CP1 SD1 Q1 Q1 12345678 CD1 J1 K1 CP1 SD1 Q1 Q1 GND Figure 1. Pinout; 16−Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN FUNCTION J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs http://onsemi.com 16 1 16 1 16 1 DIP−16 N SUFFIX CASE 648 SO−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F 16 1 EIAJ−16 M SUFFIX CASE 966 ORDERING INFORMATION Device Package Shipping MC74AC109N PDIP−16 25 Units/Rail MC74ACT109N PDIP−16 25 Units/Rail MC74AC109D SOIC−16 48 Units/Rail MC74ACT109D SOIC−16 48 Units/Rail MC74AC109DR2 SOIC−16 2500 Tape & Reel MC74ACT109DR2 SOIC−16 2500 Tape & Reel MC74AC109DT TSSOP−16 96 Units/Rail MC74ACT109DT TSSOP−16 96 Un...