PLL602-04

m Preliminary for proposal PLL602-04 o c . Low Phase Noise CMOS XO (96MHz to 200MHz) U t4 e FEATURES PIN CONFIGURATION e h XO for the 96MHz to 200MHz Low phase noise S range (-125 ta dBc at 10kHz offset). CMOS a output. 12 to .D25MHz crystal input. Integrated crystal load capacitor: no external w load capacitor required. w Low jitter (RMS): 9-12ps period jitter (1 sigma). w 3.3V operation. CLK 1 2 3 4 8 7 6 5 GND PLL602-04 VDD OE GND N/C Available in 8-Pin TSSOP or SOIC. DESCRIPTIONS The PLL602-04 is a low cost, high performance and low phase noise XO, providing less than -125 dBc at 10kHz offset in the 96MHz to 200MHz operating range. The very low jitter (9 to 12 ps RMS period jitter) makes this chip ideal for 155.52MHz SONET and SDH applications, and for 125MHz and 106.25MHz applications. Input crystal can range from 12 to 25MHz (fundamental resonant mode). BLOCK DIAGRAM XIN XOUT m o .c U 4 t e e h S a t a .D w w w OUTPUT RANGE MULTIPLIERS FREQUENCY RANGE XIN XOUT OUTPUT BUFFER x8 96 - 200MHz CMOS VCO Divider Reference Divider Phase Comparator Charge Pump Loop Filter VCO CLK XTAL OSC 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 m o .c 4U t e e h S a t a D . w w w OE Rev 12/04/01 Page 1 Preliminary for proposal PLL602-04 Low Phase Noise CMOS XO (96MHz to 200MHz) PIN DESCRIPTIONS Name CLK VDD OE XIN XOUT N/C GND Number 1 2 3 4 5 6 7, 8 Type O P I I I P Output clock pin. +3.3V VDD power supply...