Low Phase Noise XO
m Preliminary for proposal PLL602-01 o c . Low Phase Noise XO (24MHz to 50MHz) U t4 e FEATURES PIN CONFIGURATION e h XO ...
Description
m Preliminary for proposal PLL602-01 o c . Low Phase Noise XO (24MHz to 50MHz) U t4 e FEATURES PIN CONFIGURATION e h XO output for the 24MHz to Low phase noise S 50MHz range ta (-135 dBc at 10kHz offset). CMOS a output. 12 to .D25MHz crystal input. Integrated crystal load capacitor: no external w load capacitor required. w Low jitter (RMS): 5-7ps period jitter (1 sigma). w 3.3V operation.
CLK 1 2 3 4 8 7 6 5 GND
PLL602-01
VDD OE
GND
N/C
Available in 8-Pin TSSOP or SOIC.
DESCRIPTIONS
The PLL602-01 is a low cost, high performance and low phase noise XO, providing less than -135dBc at 10kHz offset in the 24MHz to 50MHz operating range. The very low jitter (5 ps to 7 ps RMS period jitter) makes this chip ideal for applications requiring reference frequency sources. Input crystal can range from 12 to 25MHz (fundamental resonant mode).
BLOCK DIAGRAM
XIN XOUT
m o .c U 4 t e e h S a t a .D w w w
OUTPUT RANGE
MULTIPLIER FREQUENCY RANGE
XIN
XOUT
OUTPUT BUFFER
x2
24 - 50MHz
CMOS
VCO Divider
Reference Divider
Phase Comparator
Charge Pump
Loop Filter
VCO
CLK
OE
XTAL OSC
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
m o .c 4U t e e h S a t a D . w w w
Rev 12/04/01 Page 1
Preliminary for proposal
PLL602-01
Low Phase Noise XO (24MHz to 50MHz)
PIN DESCRIPTIONS
Name
CLK VDD OE XIN XOUT N/C GND
Number
1 2 3 4 5 6 7, 8
Type
O P I I I P Output clock pin. +3.3V VDD power supply pin.
Description
Output enable inp...
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