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FEATURES
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Low phase noise (-130 dBc @ 10kHz offset). CMOS output with OE tri-state control. Selectable oscillator “on” or “off” feature in output disable mode Ultra Low current consumption (<2.5mA, <2mA, <1.3mA at 27MHz respectively for PLL600-17, PLL600-27, and PLL600-37) Ultra Low disable mode current (<2uA when disabled with osc. off) 10 to 52MHz fundamental crystal input. Selectable divider by 2 (PLL600-17 only). 12mA drive capability at TTL output. Low jitter (RMS): 2.5ps period jitter. 2.25V to 3.63V DC operation. Available in 8 pin SOIC, 6 pin SOT or DIE.
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Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
PIN ASSIGNMENT (PACKAGE)
8 pin SOIC
XIN SEL*^ GND OSCSEL^
* Note: ^:
4U
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m o c
Preliminary
PLL600-17/-27/-37
1 2 3 4
8 7 6 5
XOUT OE^ VDD CLK
pin2 is SEL for PLL600-17 pin2 is N/C for PLL600-27/-37 denotes internal pull-up
6 pin SOT
CLK
DESCRIPTION
The PLL600-17/-27/-37 form a low cost family of XO IC’s, designed to consume the lowest current on the market for the 5MHz to 52MHz range. It accepts input crystal from 10 to 52MHz (fundamental resonant mode) and offers a selectable divider by 2 (PLL600-17 only) or no division. Providing less than -130dBc at 10kHz offset at 30MHz, and with a very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring low current frequency sources, such as handheld devices.
BLOCK DIAGRAM
SEL
Reference Divider
XIN XOUT
XTAL OSC
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OE
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S a
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GND
U 4
1 2 3 XIN
1 2 3 4
.c
PLL600-x7
8
^: denotes internal Pull-up
PAD ASSIGNMENT (DIE)
SELECTION TABLE
CLK
SEL (PLL600-17 only) DIVIDER
PLL600-x7
m o
6 5 4
VDD OE^ XOUT
7 6 5
0 1
/2 No division
OSCSEL
Internal Pull-up, default value is ‘1’ when not connected. Selectable divider only available on P600-17.
OE
OSCSEL
OUTPUT
0 0 1 1
0 1 0 1
Internal Pull-up, default value is ‘1’ when not connected. Not available in 6 pin SOT package.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
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Disabled - osc. off Disabled - osc. on Enabled Enabled
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Rev 9/23/03 Page 1
Preliminary
PLL600-17/-27/-37
Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
PIN DESCRIPTION
Name
XOUT SEL GND OSCSEL CLK VDD OE XIN
Pin # 8 pin
1 2 3 4 5 6 7 8
Die Pad Position X ( µ m)
94.183 94.157 94.183 94.193 715.472 715.307 715.472 715.472
6 pin
4 n/a 2 n/a 1 6 5 3
Y ( µ m)
768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881
Type
I I P I O P I I
Description
Crystal output pin. PLL600-17 only: select pin. See Table on page 1. PLL600-27/-37: no connect Ground pin. Disable mode select pin. See Table on page 1. Output clock pin. +3.3V VDD power supply pin. Output Enable input pin. See Table on page 1. Crystal input pin.
SEL and OSCSEL have internal pull-ups, so the default value is ‘1’ when not connected (not available on 6 pin package).
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature Storage Temperature Ambient Operating Temperature* TS -65 0
SYMBOL
V CC VI VO
MIN.
MAX.
7 V CC + 0.5 V CC + 0.5 260 150 70
UNITS
V V V °C °C °C
- 0.5 - 0.5 - 0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 9/23/03 Page 2
Preliminary
PLL600-17/-27/-37
Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
2. AC Electrical Specifications PARAMETERS
Input Crystal Frequency At power-up (Vdd reaches 2.2V) Disable to enable, osc. Off Disable to enable, osc. On Output Clock Rise/Fall Time VDD sensitivity Output Clock Duty Cycle Short Circuit Current
Note: (*) Preliminary Specifications still to be characterized.
CONDITIONS
MIN.
10
TYP.
MAX.
52
UNITS
MHz ms ms
10* 10* 500* 1.15 3.7 0.8 45 50 ± 50 0.8 55
Settling time
µs ns ppm % mA
0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load Frequency vs. VDD +/- 10% Measured @ 1.4V
3. Jitter and Phase Noise specification PARAMETERS
RMS Period Jitter (1 sigma – 1000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling between VDD and GND. 30MHz @100Hz offset 30MHz @1kHz offset 30MHz @10kHz offset 30MHz @100kHz offset 30MHz @1MHz offset
MIN.
TYP.
2.1 -80 -110 -130 -138 -145
MAX.
2.5
UNITS
ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 9/23/03 Pag.