PLL602-39

m Preliminary PLL602-35/-37/-38/-39 o c . 750kHz – 800MHz Low Phase Noise Multiplier XO U Universal Low Phase Noise IC’s 4 t e FEATURES e PIN CONFIGURATION h (Top View) S to 800MHz range. Selectable 750kHz a t noise output (@ 10kHz frequency Low phase offset, a -140dBc/Hz for 19.44MHz, -127dBc/Hz for D -125dBc/Hz for 155.52MHz, 106.25MHz, . 110dBc/Hz for 622.08MHz). w w CMOS (PLL602-37), PECL (PLL602-35 and or LVDS (PLL602-39) output. w PLL602-38) 12 to 25MHz crystal input. VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND XIN PLL 602-3x No external load capacitor or varicap required. Output Enable selector. Selectable 1/16 to 32x frequency multiplier. 3.3V operation. Available in 16-Pin (TSSOP or 3x3mm QFN). DESCRIPTIONS The PLL602-35 (PECL with inverted OE), PLL602-37 (CMOS), PLL602-38 (PECL), and PLL602-39 (LVDS) are high performance and low phase noise XO IC chips. They provide phase noise performance as low as –125dBc at 1kHz offset (at 155MHz), by multiplying the input crystal frequency up to 32x. They accept fundamental parallel resonant mode crystals from 12 to 25MHz. BLOCK DIAGRAM SEL X+ X- Oscillator Amplifier m o .c U 4 t e e h S a t a .D w w w SEL3^ SEL2^ OE GND GND XOUT CLKC VDD CLKT GND GND SEL0^ / VDD* VDD / GND* XOUT 12 11 10 9 SEL1^ XIN 13 8 7 6 5 GND CLKC VDD CLKT SEL3^ SEL2^ OE 14 15 PLL602-3x 1 2 3 16 4 GND GND GND ^: *: Internal pull-up On 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin...