PLL650-06

FEATURES w w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. One output fixed at 50MHz One selectable frequency output of 66.6 or 75MHz (with Double Drive Strength output). Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150mil SOIC. .D at h S a t e e 4U . m o c PLL650-06 Network LAN Clock PIN CONFIGURATION XIN XOUT GND 50MHz/FS* 1 2 3 4 8 7 6 5 VDD GND 75MHz+/66MHz+ VDD PLL650-06 *: bi-directional pin + : double strength output FREQUENCY TABLE FS DESCRIPTIONS The PLL 650-06 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces one 50MHz output clock and one selectable 75MHz or 66.6MHz output clock, making the chip ideal for networking applications. BLOCK DIAGRAM XIN XOUT XTAL OSC FS w w w .D t a S a e h t e 1 0 U 4 .c m o Pin 6 75MHz 66.6MHz 50MHz Control Logic 1 75MHz/66MHz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 w w w .D at h S a t e e 4U . m o c Rev 08/15/03 Page 1 PLL650-06 Network LAN Clock PIN DESCRIPTIONS Name XIN XOUT 50MHz/FS 75MHz / 66MHz VDD GND Number 1 2 4 6 5, 8 3, 7 Type I I B O P P Description 25MHz fundamental crystal input (20pF C...