MT46V2M32

4U t DOUBLE eDATA RATE e h (DDR) S SDRAM a t a D . FEATURES w w w .c om PRELIMINARY 64Mb: x32 DDR SDRAM MT46V2M32V1- 512K x 32 x 4 banks MT46V2M32 - 512K x 32 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Reduced output drive option Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) for masking write data Programmable burst lengths: 2, 4, 8, or full page 32ms, 4,096-cycle auto refresh (7.8µs/cycle) Auto precharge option Auto Refresh and Self Refresh Modes Programmable I/O (SSTL_2 compatible) – reduced and impedance matched PIN ASSIGNMENT (TOP VIEW) 100-Pin TQFP (Normal Bend Shown) OPTIONS Configuration 2 Meg x 32 (512K x 32 x 4 banks) Power Supply 2.5V VDD/VDDQ 2.65V VDD/VDDQ Plastic Package 100-pin TQFP (0.65mm lead pitch) Timing - Cycle Time 200 MHz @ CL = 3 183 MHz @ CL = 3 166 MHz @ CL = 3 150 MHz @ CL = 3 MARKING w w w .D t a LG -5 -55 -6 -65 S a e h 2M32 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 WE...