CYP15G04K200

m o .c U 4 t e e h S Features a at .D w w w Programmable Serial Interface PRELIMINARY (High Speed Devices) Programmable Bandwidth Power-saving mode Up to two serial channels available to allow: — High-Bandwidth — Redundancy Supported standards: — InfiniBand™ — SONET OC-48 200 Mbps – 1.5 Gbps, 2.5 Gbps serial signaling rate Flexible parallel-to-serial conversion in transmit path Flexible serial-to-parallel conversion in receive path Multiple selectable loopback/loop-through modes 100K to 200K usable gates of CPLD logic 240K to 480 Kb of integrated memory — 192K to 384Kb of synchronous or asynchronous SRAM — 48K to 96Kb of true Dual-Port or FIFO RAM Internal transmit and receive PLLs Logic dedicated Spread Aware PLL Transmit FIFO for flexible variable phase clocking Differential CML serial input with internal termination and DC-restoration Differential CML serial output with source matched impedance of 50Ω 160–240 user programmable I/Os Any Volt™ I/O interface — Programmable as 1.8V, 2.5V, 3.3V Multiple I/O standards — LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II), HSTL(I-IV), and GTL+ Direct interface to standard fiber-optic modules Designed to drive: — Fiberoptic Modules — Copper Cables — Circuit Board Traces — Backplane Links — Box-to-Box Links — Chip-to-Chip Communication Extremely flexible clocking options — Four global clocks — Up to 192 additional product term clocks — Clock polarity at every register Carry chai...