ADSP2195

35(/,0,1$5< 7(&+1,&$/ '$7$ a U 4 t w w m o .c e e Preliminary Technical Data h S a at .D w ADSP-219x DSP CORE FEATURES 6.25 ns Instruction Cycle Time (Internal), for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy -to-Use Algebraic Syntax Single-Cycle Instruction Execution Up to 16M words of Addressable Memory Space with 24 Bits of Addressing Width Dual Purpose Program Memory for Both Instruction and Data Storage Fully Transparent Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle Unified Memory Space Permits Flexible Address Generation, Using Two Independent DAG Units DSP Microcomputer ADSP-2195 Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-bit Accumulators Single-Cycle Context Switch between Two Sets of Computational and DAG Registers Parallel Execution of Computation and Memory Instructions Pipelined Architecture Supports Efficient Code Execution at Speeds up to 160 MIPS Register File Computations with All Nonconditional, Nonparallel Computational Instructions Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution Architectural Enhancements for Compiled C Code Efficiency FUNCTIONAL BLOCK DIAGRAM ,1 7( 55 83 7 & 21 75 2/ /( 5 7,0 ( 56 )/$* 6 %/2&. &$&+( ×  % ,7 '$* ×× '$* × ×  352*5$0 6( 4 8 ( 1& ( 5 30 $''5( 66 %86  '0 $' ' 5 (6 6 % 8 6 30 '$7$ %86 %86 &211(&7 3; '0 '$7$ %86 '$7$ 5( *,67 (...