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TM320240AKGWT Dataheets PDF



Part Number TM320240AKGWT
Manufacturers TIANMA
Logo TIANMA
Description LCD_Module
Datasheet TM320240AKGWT DatasheetTM320240AKGWT Datasheet (PDF)

w w w t e e h SPECIFICATION FOR LCD MODULE S a t a D . Model No. TM320240AKGWT 4U . m o c Prepared by: Checked by : Verified by : Approved by: w w w .D t a S a e h Date: Date: t e U 4 .c m o Date: Date: TIANMA MICROELECTRONICS CO., LTD h w w w .D a S a t t e e 4U . m o c Ver. 1.0 REVISION RECORD Date Ver. Ref. Page Revision No. Revision Items 1/22 1. General Specifications: 1.1 Display type: COLOR STN 1 1.2 Display color* : Display color: Decided by the Contro.

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w w w t e e h SPECIFICATION FOR LCD MODULE S a t a D . Model No. TM320240AKGWT 4U . m o c Prepared by: Checked by : Verified by : Approved by: w w w .D t a S a e h Date: Date: t e U 4 .c m o Date: Date: TIANMA MICROELECTRONICS CO., LTD h w w w .D a S a t t e e 4U . m o c Ver. 1.0 REVISION RECORD Date Ver. Ref. Page Revision No. Revision Items 1/22 1. General Specifications: 1.1 Display type: COLOR STN 1 1.2 Display color* : Display color: Decided by the Controller Background*2: Black (Red, Green, Blue dots are off state) 1.3 Polarizer mode: Transmissive/Negative 1.4 Viewing Angle: 6:00 1.5 Driving Method: 1/240 Duty 1/17 Bias 1.6 Backlight Type: CCFL Backlight Color: WHITE Backlight Life: 15000 hrs (Min.) 1.7 Driver: LH1562F4 1.8 Data Transfer: 8 Bit Parallel 1.9 Operating Temperature: -10----+60¡æ Storage Temperature: -20----+70¡æ 1.10 Power Supply Voltage: VDD=5.0V 1.11 LCD Operating Voltage: VLCD=23.0V 1.12 Outline Dimensions: Refer to outline drawing on next page 1.13 Dot Matrix: 320 X 3(RGB) X 240 Dots 1.14 Dot Size: 0.345(R+G+B)¡Á 0.345(mm2) 1.15 Dot Pitch: 0.36¡Á 0.36 (mm2) 1.16 Weight: TBD*3 *1 Color tone is slightly changed by temperature and driving voltage. *2 Color tone will be changed by backlight. *3 TBD: To Be Determined. 2/22 2. Outline Drawing 3/22 3. LCD Module Part Numbering System TM 320240 A K G W T IC PACKAGE T: TAB TEMPRATURE RANGE W: WIDE TEMPERATURE RANGE BACKLIGHT TYPE G: TRANSMISSIVE, CCFL BACKLIGHT LCD TYPE K: COLOR STN MODE NEGATIVE MODULE SERIES MODULE TYPE DIGITS INDICATING: 320 (RGB) COLUMNS X 240 ROWS T: TIANMA M: MODULE 4/22 4. Circuit Block Diagram 5/22 5. Absolute Maximum Ratings Item Power Supply Voltage LCD Driving Voltage Operating Temperature Range Storage Temperature Range Symbol VDD£- VSS VLCD TOP Min. -0.3 -0.3 -10 Max. +6.0 V +40.0 +60 ¡æ TST -20 +70 Unit Ta=25¡æ Remark No Condensation 6/22 6. Electrical Specifications and Instruction Code 6.1 Electrical characteristics Item Supply Voltage (Logic) Supply Voltage (LCD Drive) High £¨ Low £¨ Symbol VDD-Vss Min. Vss=0V, Ta=25¡æ Typ. Max. Unit +4.5 +5.0 +5.5 V VLCD VIH VDD=5.0£© VIL VDD=5.0£© IDD (VDD- VSS=5.0V) - 23.0 - V Input Signal Voltage 0.8VDD - VDD V 0 - 0.2 VDD V Supply current (Logic) Supply current (LCD Drive) Supply Voltage (CCFL Drive) Supply current (CCFL Drive) Frequency (CCFL Drive) - 1.5 - mA IEE VCL (ICL=5.0mA) ICL - 4.5 - mA - 270 350 Vrms - 5.0 6.3 mArms fCL - 36.6 - kHz 7/22 6.2 Interface Signals 6.2.1 CON1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol M YD LP XCK DISPOFF Level H/L H/L H/L H/L H/L 0V +23V H/L H/L H/L H/L H/L H/L H/L H/L Description Input of signal to AC electrify the liquid crystal drive output Scan start pulse Display data latch pulse input Display data shift clock input H: Display on, L: Display off Ground LCD voltage input Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 VDD VSS VEE D7 D6 D5 D4 D3 D2 D1 D0 +5.0V Supply voltage for logic 6.2.2 CON2 Pin No. 1 2 3 Symbol VFL1 NC VFL2 Level AC VSS Description Supply voltage for CCFL No connection Supply voltage for CCFL 8/22 6.3 Interface Timing Chart 6.3.1 Segment mode tWLPH LP tLD tLS XCK tR tWCK DI7-DI0 LAST DATA tWDL  tSD tF tDS TOP DATA tDH tSL tLH tWCKH tWCKL (VSS = V5 = 0 V, VDD = +5.0±0.5 V, V0 = +15.0 to +42.0 V, TOPR = –20 to +85 ˚C) PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time  removal time  "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tS tR tF tSD tWDL tD tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 30 1.2 1.2 CONDITIONS tR, tF ≤ 10 ns MIN. 50 15 15 10 12 15 0 30 25 25 10 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs 2 2 NOTE 1 NOTES : 1. Takes the cascade connection into consideration. 2. (tWCK – tWCKH – tWCKL)/2 is maximum in the case of high speed operation. 9/22 6.3.2 Common Mode tWLP LP tR tWLPH tSU tF tH EIO2 tDL EIO1 tWDL  tSD FR tPD1 LP tPD2  tPD3 Y1-Y240 [L/R = "L"] (VSS = V5 = 0 V, VDD = +2.5 to +5.5 V, V0 = +15.0 to +42.0 V, TOPR = –20 to +85 ˚C) PARAMETER Shift clock period Shift clock "H" pulse width Data setup time Data hold time Input signal rise time Input signal fall time  removal time  "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL tWLP tWLPH tSU tH tR tF tSD tWDL tDL tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 200 1.2 1.2 CONDITIONS tR, tF ≤ 20 ns VDD = +5.0±0.5 V MIN. 250 15 30 50 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns µs ns µs .


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