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CS8553 Dataheets PDF



Part Number CS8553
Manufacturers Myson Technology
Logo Myson Technology
Description TV Encoder
Datasheet CS8553 DatasheetCS8553 Datasheet (PDF)

GENERAL DESCRIPTION The CS8553 provides full conversion from digital video format YCbCr into NTSC/PAL composite. It can be used in VCD, DVD, and digital VCR applications. Two times oversampling reduces the output filter requirements and guarantees no alias interference by internal UV filters and Y filter. A 9-bit DAC provides a composite video output with high quality image. 32-pin package and pin assignment make the CS8553 compatible with major vendors. w w w .D at aS e e h U 4 t . m .

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GENERAL DESCRIPTION The CS8553 provides full conversion from digital video format YCbCr into NTSC/PAL composite. It can be used in VCD, DVD, and digital VCR applications. Two times oversampling reduces the output filter requirements and guarantees no alias interference by internal UV filters and Y filter. A 9-bit DAC provides a composite video output with high quality image. 32-pin package and pin assignment make the CS8553 compatible with major vendors. w w w .D at aS e e h U 4 t . m o c TV Encoder FEATURES CS8553 • Especially designed for VCD, Karaoke, digital VCR, DVD, DIGITAL set-top box. • Supports the following 4 modes: NTSC, PAL-M, PAL-BDGHI, PAL-Nc. • 8-bit 4:2:2 YCbCr inputs for glueless interface to MPEG decoders. • CVBS (composite YC) outputs. • Supports CCIR-601 format, non-square pixel • 2x oversampling simplifying external filtering. • 6MHz and 1.3MHz anti-alias filters for Y and U/V channels each. • 1 channel of 9-bit DAC. • Supports master and slave modes. • Supports interlace operation only. • Automatic mode detection/switching in slave mode. • 3.3V supply voltage; 5V tolerant for all digital I/O pins. BLOCK DIAGRAM H, V-SYNC VIDEO-TIMING CONTROLLER CLK_27 SLEEP P[7:0] MODE[3:0] SVIDEO MASTER CBSWAP w w SERIAL TO w .D t a 4:4:4 INTER- S a e h u-FILTER t e U 4 .c m o SUB-CARRIER GENERATION SINE-TABLE 4:2:2 to v-FILTER COLOR-BURST & MODULATION & MIXER CVBS/Y DAC PARALLEL POLATION y-FILTER DACMAPPING VREF_O FSADJUST COMP Myson Century, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 USA: 1485 Saratoga Ave. #200 San Jose, CA, 95129 Tel: 408-973-8388 Fax: 408-973-9388 w w w .D at h S a t e e 4U . m o c [email protected] www.myson.com.tw Rev. 1.3 January 2003 page 1 of 21 CS8553 PIN CONNECTION DIAGRAM CVBS/Y 32 31 30 29 28 27 26 FADJI COMPI VAA VREFO VREFI NC NC VSS 25 CLK_27 HSYNC VSYNC VDD VSS VSS VSS 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9 24 23 22 21 20 19 18 17 P7 P6 P5 P4 P3 P2 P1 P0 CS8553T SVIDEOI CBSWAPI MASTERI SLEEP MD3 MD2 MD1 Figure-1 32-pin TQFP MD0 page 2 of 21 CS8553 PIN DESCRIPTION Name CLK_27 VSYNC HSYNC P[7:0] I/O I I/O I/O I TQFP Pin No. 25 28 29 24-17 Description Pixel clock, 27MHz, twice the Y sample rate Vertical sync, output in master mode or input in slave mode, is synchronized by CLK. Horizontal sync, output in master mode or input in slave mode, is synchronized by CLK too. YCbCr pixel inputs (TTL compatible). Also, synchronized by CLK with respect to the incoming HSYNC timing, the higher index corresponds to a greater significance. Configuration inputs in 0: slave mode, h and v sync are inputs. 1: master mode, h and v sync are outputs. 0: normal Cr, Cb sequence. 1: swaps Cr, Cb sequence Connected to VSS. 1: power down, reset 0: normal operation Full scale adjust control pin. A resistor RSET is connected to GND. Used to control the full-scale output current on analog outputs. Compensation pin. A 0.1µF capacitor is used to bypass this pin to VCC. Voltage reference output, typically 1.2V, may be used to connect to VREFI input. Voltage reference input, typically 1.235V. A 0.11µF capacitor must be used to decouple this input to GND. DAC current switch reference input, connect to VREFO output. No connection No connection Composite output or luminance (with blanking and sync) Analog power Digital power Digital ground Analog ground Analog ground MD[3:0] MASTER CBSWAP SVIDEO SLEEP FSADJUST COMP VREFO VREFI/VRDAC I I I I I I I I I 13-16 12 11 10 9 1 2 4 5 NC NC CVBS/Y VAA VDD GND AGND VSS O O O 6 7 32 3 27 26 31,8 30 page 3 of 21 CS8553 FUNCTIONAL DESCRIPTION MODE configuration SeeTable 1 to Table 3 for details. master = 1: master mode Horizontal sync and vertical sync are generated from internal timing and are output at the rising edge of clk_27. md[3]: Defines EFIELD function 0: vsync is output pin 1: vsync is even/odd field indicator, vsync=0 even, vsync=1 odd. md[2]: Defines PAL625 function 0: 525-line operation is set. 1: 626-line operation is set. master = 0: slave mode Horizontal sync and vertical sync are inputs that are synchronized by clk_27. A falling edge of VSYNC* occurring within ±1/4 of a scan line from the falling edge of HSYNC* cycle time indicates the beginning of Field-1. A falling edge of VSYNC* occurring within ±1/4 of a scan line from the middle point of the line indicates the beginning of Field-2. See Figure 2. Field-1 Field-2 Figure-2 md[3]: Defines YCSWAP 0: normal operation. 1: Swap the luma and chroma samples. md[2]: Defines SETUP function 0: 7.5 IRE setup is enabled for NTSC and PAL-M, with scaling for 92.5% black-to-white range, other PALs with normal 100% black-to-white range. 1: 7.5 IRE setup is disabled for NTSC and PAL-M, with scaling for 100% black-to-white range. md[1]: Defines PALSA function, South America. 0: Normal operation. 1: PAL-M used for Brazil 525 lines operatio.


CS8552 CS8553 D1073


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