Century Semiconductor Inc. om
GENERAL DESCRIPTION
w
w
BLOCK DIAGRAM
HOL
CONTROLLER SERIAL TO
H, V-SYNC
VIDEO-TIMING
PL
t a S a
SUB-CARRIER GENERATION u-FILTER 4:2:2 to 4:4:4 INTERPOLATION v-FILTER y-FILTER FSADJUST
CLK_27 SLEEP
3U
P[7:0]
MODE[3:0] SVIDEO MASTER CBSWAP
w
w
PARALLEL
w
.D
QD
e h t e
VBIAS VREF_O
U\
U 4 .c
SINE-TABLE COLOR-BURST & MODULATION & MIXER DACMAPPING COMP
CS8552 provides full conversion from digital video format YCbCr into NTSC/PAL composite and Svideo. It can be used in VCD, DVD, digital VCR application. Two-times oversampling reduces the output filter requirements and guarantees no alias interference by internal UV filters and Y filter. Two 9-bit DACs provides two channels for a Svideo output port or two composite video outputs with high quality of image. 32-pin package and pin assignment make CS8552 compatible with major vendors.
w
.D
a
S a t
e e h
U 4 t
.c
CS8552 TV Encoder
FEATURES • Designed special for VCD, Karaoke, digital VCR, DVD, DIGITAL set-top box. • Support the following 4 modes: NTSC, PAL-M, PAL-BDGHI, PAL-Nc • 8-bit 4:2:2 YcbCr inputs for glueless interface to MPEG decoders • CVBS (composite YC) or S-video (Y and C) outputs • Support CCIR-6-1 for mat, non-square pixel • 2x oversampling simplify external filtering • 6MHz and 1.3MHz anti-alias filters for Y and U/V channels each • On-chip color bar generation • 2 channels of 9-bit DAC • Support master and slave modes • Support interlace operation only • Automatic mode detection/switching in slave mode • 3.3V supply voltage; 5V tolerant for all digital I/O pins
m o
CVBS/Y
CVBS/C
Century Semiconductor, Inc. Taiwan: No. 2, Industry East Rd. 3rd, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
USA: 1485 Saratoga Ave. #200 San Jose, CA, 95129 Tel: 408-973-8388 Fax: 408-973-9388
w
w
w
.D
at
[email protected] [email protected] www.century-semi.com Rev.0.1 May 2001 page 1 of 23
h S a
t e e
4U
.
m o c
Century Semiconductor Inc.
PIN CONNECTION DIAGRAM
CS8552
CLK_27M
P7
P6
P5
P4
P3
P2
P1 22
29
28
27
26
25
24
23
21
P0
VSS VDD VSYNC HSYNC NC VSS CVBSY
30 31 32 1 2 3 4
20 19 18 17 16 15 14
MD0 MD1 MD2 MD3
CS8552
QD PL
10 12 CVBSC VDD 11 6 7 8 9 VBIAS VSS COMPI
3U
HOL
Figure-1 32-pin PLCC
VREFO
SLEEP
FADJI
VREFI
13
5
U\
MASTERI CBSWAPI SVIDEOI page 2 of 23
Century Semiconductor Inc.
PIN DESCRIPTION
Name CLKI VSYNC HSYNC P[7:0] I/O I I/O I/O I Pin 29 32 1 28-21 Description Pixel clock, 27MHz, twice the Y sample rate
CS8552
Vertical sync, output in master mode or input in slave mode, is synchronized by CLK. Horizontal sync, output in master mode or input in slave mode, is synchronized by CLK too. YCbCr pixel inputs (TTL compatible). Also, synchronized by CLK with respect to the incoming HSYNC timing, the higher index corresponds to a greater significance. Configuration inputs in 0: slave mode, h and v sync are inputs. 1: master mode, h and v sync are outputs. 0: normal Cr, Cb sequence. 1: swaps Cr, Cb sequence 0: composite output same signal on both Y, C channels, 1: s-video output, Y, C channels. 1: power down, reset 0: normal operation
MD[3:0] MASTER CBSWAP SVIDEO SLEEP FSADJUST COMP VREFO VREFI/VRDAC
I I I I I I I I I
17-20 16 15 14 13 5 6 8 9
Full scale adjust control pin. A resistor is connected to GND. Used to control the full-scale output current on analog outputs. Compensation pin. A 0.1µF capacitor is used to bypass this pin to VCC. Voltage reference output, typically 1.2V, may be used to connect to VREFI input.
VBIAS CVBS/C CVBS/Y VAA VDD GND AGND NC
O O O
10 11 4
3U
3, 12 2
HOL
7 Analog power 31 Digital power 30 Digital ground Analog ground No connection
PL
Voltage reference input, typically 1.235V. A 0.11µF capacitor must be used to decouple this input to GND. DAC current switch reference input, connect to VREFO output. DAC bias voltage, 0.7 v less than COMP signal
Composite output or chrominance Composite output or luminance (with blanking and sync)
QD
U\
page 3 of 23
Century Semiconductor Inc.
FUNCTIONAL DESCRIPTION MODE configuration SeeTable 1 to Table 3 for details. master = 1: master mode
CS8552
horizontal sync and vertical sync are generated from internal timing and are output at the rising edge of clk_27. md[3]: define EFIELD function 0: vsync is output pin 1: vsync is even/odd field indicator, vsync=0 even, vsync=1 odd. md[2]: define PAL625 function 0: 525 line operation is set. 1: 626 line operation is set. master = 0: slave mode Horizontal sync and vertical sync are inputs that are synchronized by clk_27. A falling edge of VSYNC* occurring within ±1/4 of a scan line from the falling edge of HSYNC* cycle time indicates the beginning of Field-1. A falling edge of VSYNC* occurring within ±1/4 of a scan line from the middle point of the line indicates the beginning of Field-2. See Figure 2
Field-1
md[3]: define YCSWAP 0: normal operation. 1: Swap the luma and chroma sa.