25PPC405EP

Preliminary www.DataSheet4U.com PowerPC 405EP Embedded Processor Data Sheet Features IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz with 16KB D- and Icaches PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications 4KB on-chip memory (OCM) Programmable timers External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8- or 16-bit SRAM and external peripherals - Up to five devices DMA support for memory and UARTs. - Scatter-gather chaining supported - Four channels PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Asynchronous PCI Bus interface Software accessible event counters Two serial ports (16750 compatible UART) One IIC interface General purpose I/O (GPIO) available Supports JTAG for board level testing Internal processor local Bus (PLB) runs at SDRAM interface frequency Supports PowerPC processor boot from PCI memory - Internal or external PCI Bus Arbiter Two Ethernet 10/100Mbps (full-duplex) ports with media independent interface (MII) Programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive interrupts Description Designed specifically to address embedded applications, the PowerPC 405EP (PPC405EP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-p...