CYD04S72V

PRELIMINARY CYD04S72V CYD09S72V CYD18S72V FLEx72™ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features True dual-ported memory cells that allow simultaneous access of the same memory location Synchronous pipelined operation Family of 4-Mbit, 9-Mbit and 18-Mbit devices Pipelined output mode allows fast operation 0.18-micron CMOS for optimum speed and power High-speed clock to data access 3.3V low power — Active as low as 225 mA (typ) — Standby as low as 55 mA (typ) Mailbox function for message passing Global master reset Separate byte enables on both ports Commercial and industrial temperature ranges IEEE 1149.1-compatible JTAG boundary scan 484-ball FBGA (1 mm pitch) Counter wrap around control — Internal mask register controls counter wrap-around — Counter-interrupt flags to indicate wrap-around — Memory block retransmit operation Counter readback on address lines Mask register readback on address lines Dual Chip Enables on both ports for easy depth expansion Seamless Migration to Next Generation Dual Port Family Functional Description The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal ...