UPD27C8001DZ-15

********** -TOP VIEW- C-MOS 8M(1048,576x8)-BIT ERASABLE PROM w w t a A16 .D w A15 A19 A12 A7 A6 A5 A4 A3 A2 A1 A0 IN IN IN IN IN IN IN IN IN aS e e h U 4 t m o .c 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 31 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 UPD27C8001DZ-15(1/2) IL08 1 2 3 4 5 6 7 8 9 VDD 32 (+5V) 31 30 29 28 27 26 25 24 23 22 A18 IN A17 IN A14 IN A13 IN A8 A9 IN IN O0 O1 O2 O3 O4 O5 O6 O7 A11 IN OE /V PP IN A10 IN IN 10 IN 11 IN 12 O0 OUT 13 O1 OUT 14 O2 OUT 15 w 16 GND w w t a .D 21 20 19 18 17 S a CE IN e h U 4 t e .c m o 13 14 15 17 18 19 20 21 CE OE /V PP 22 24 O7 OUT O6 OUT O5 OUT O4 OUT O3 OUT A0-A19 O0-O7 CE OE /V PP ;ADDRESS INPUTS ;DATA OUTPUTS ;CHIP ENABLE ;OUTPUT ENABLE/PROGRAM VOLTAGE w w w .D a t a e h S 4 t e U m o .c UPD27C8001DZ-15(2/2) 32 V DD 16 DATA OUTPUTS O0-07 GND 13 OE /VPP CE 24 22 15 17 21 OUTPUT ENABLE/ PROGRAM VOLTAGE CHIP ENABLE OUTPUT BUFFERS 12 A0 Y DECODER Y GATING ADDRESS INPUTS X DECODER 1 A19 8388608 BITS (2048X4096) MEMORY CELL ARRAY ABOVE DIAGRAM SHOWS CONDITIONS BEFORE PROGRAMMING. SYMBOL MODE READ OUTPUT DISABLE STANDBY PROGRAM PROGRAM VERIFY PROGRAM INHIBIT 1 0 X HI-Z CE 0 0 1 0 0 1 OE /V PP 0 1 X +12.5 0 +12.5 V DD +5V O0-O7 D OUT HI-Z HI-Z D IN D OUT HI-Z +6.5V ;HIGH LEVEL ;LOW LEVEL ;DON'T CARE ;HIGH IMPEDANCE ...