MT4C4M4E8

TECHNOLOGY, INC. 4 MEG x 4 EDO DRAM MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9 DRAM FEATURES Industry-standard x4 pinout, timing, functions and packages State-of-the-art, high-performance, low-power CMOS silicon-gate process Single power supply (+3.3V ±0.3V or +5V ±10%) All inputs, outputs and clocks are TTL-compatible Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR) Optional Self Refresh (S) for low-power data retention 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) Extended Data-Out (EDO) PAGE MODE access cycle 5V-tolerant inputs and I/Os on 3.3V devices PIN ASSIGNMENT (Top View) 24/26-Pin SOJ (DA-2) VCC DQ1 DQ2 WE# RAS# *NC/A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS# OE# A9 A8 A7 A6 A5 A4 VSS 24/26-Pin TSOP (DB-2) VCC DQ1 DQ2 WE# RAS# *NC/A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS# OE# A9 A8 A7 A6 A5 A4 VSS OPTIONS Voltages 3.3V 5V Refresh Addressing 2,048 (i.e. 2K) Rows 4,096 (i.e. 4K) Rows Packages Plastic SOJ (300 mil) Plastic TSOP (300 mil) Timing 50ns access 60ns access Refresh Rates Standard Refresh Self Refresh (128ms period) MARKING LC C E8 E9 DJ TG -5 -6 None S * NC on 2K refresh and A11 on 4K refresh options. Note: The “#” symbol indicates signal is active LOW. 4 MEG x 4 EDO DRAM PART NUMBERS PART NUMBER MT4LC4M4E8DJ MT4LC4M4E8DJS MT4LC4M4E8TG MT4LC4M4E8TGS MT4...