MT4LC8M8P4

8 MEG x 8 EDO DRAM DRAM FEATURES Single +3.3V ±0.3V power supply Industry-standard x8 pinout, timing, functions, and packages 12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4) High-performance CMOS silicon-gate process All inputs, outputs and clocks are LVTTLcompatible Extended Data-Out (EDO) PAGE MODE access 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms Optional self refresh (S) for low-power data retention MT4LC8M8P4, MT4LC8M8C2 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html PIN ASSIGNMENT (Top View) 32-Pin SOJ VCC DQ0 DQ1 DQ2 DQ3 NC VCC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 32-Pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ7 DQ6 DQ5 DQ4 VSS CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 VSS OPTIONS Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) Timing 50ns access 60ns access Refresh Rates Standard Refresh (64ms period) Self Refresh (128ms period) MARKING C2 P4 DJ TG -5 -6 None S* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC VSS DQ0 DQ7 DQ1 DQ6 DQ2 DQ5 DQ3 DQ4 NC Vss VCC CAS# WE# RAS# OE# NC/A12** A0 A1 A11 A2 A10 A3 A9 A4 A8 A5 A7 VCC A6 VSS **NC on C2 version and A12 on P4 version 8 MEG x 8 EDO DRAM PART NUMBERS PART NUMBER MT4LC8M8C2DJ-x MT4LC8M8C2DJ-x S MT4LC8M8C2TG-x MT4LC8M8C2TG-x S MT...