Document
16Mb: 1 MEG x16 EDO DRAM
EDO DRAM
MT4C1M16E5 – 1 Meg x 16, 5V MT4LC1M16E5 – 1 Meg x 16, 3.3V
For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/sdramds.html
FEATURES
• JEDEC- and industry-standard x16 timing, functions, pinouts, and packages • High-performance CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or 5V ±10%) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S) • BYTE WRITE access cycles • 1,024-cycle refresh (10 row, 10 column addresses) • Extended Data-Out (EDO) PAGE MODE access • 5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View) 44/50-Pin TSOP
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC
42-Pin SOJ
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE# RAS# NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC CASL# CASH# OE# A9 A8 A7 A6 A5 A4 VSS
OPTIONS
• Voltages 1 3.3V 5V • Refresh Addressing 1,024 (1K) rows • Packages Plastic SOJ (400 mil) Plastic TSOP (400 mil) • Timing 50ns access 60ns access • Refresh Rates Standard Refresh (16ms period) Self Refresh (128ms period) • Operating Temperature Range Commercial (0oC to +70oC) Extended (-20oC to +80oC)
Part Number Example:
MARKING
LC C E5 DJ TG -5 -6 None S2 None ET
NC NC WE# RAS# NC NC A0 A1 A2 A3 VCC
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
NC CASL# CASH# OE# A9 A8 A7 A6 A5 A4 VSS
NOTE: The "#" symbol indicates signal is active LOW.
1 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER MT4LC1M16E5DJ-x MT4LC1M16E5DJ-x S MT4LC1M16E5TG-x MT4LC1M16E5TG-x S MT4C1M16E5DJ-x MT4C1M16E5TG-x Vcc REFRESH PACKAGE REFRESH 3.3V 1K 400-SOJ Standard 3.3V 1K 400-SOJ Self 3.3V 1K 400-TSOP Standard 3.3V 1K 400-TSOP Self 5V 1K 400-SOJ Standard 5V 1K 400-TSOP Standard
NOTE: “-x” indicates speed grade marking under timing options.
MT4LC1M16E5TG-6
NOTE: 1. The third field distinguishes the low voltage offering: LC designates Vcc = 3.3V and C designates Vcc = 5V. 2. Available only on MT4LC1M16E5 (3.3V)
GENERAL DESCRIPTION
The 1 Meg x 16 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function like a single CAS# found on other DRAMs in that either CASL# or CASH# will generate an internal CAS#. The CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and the last CAS# to transition back HIGH. Using only one
KEY TIMING PARAMETERS
SPEED -5 -6
tRC tRAC tPC tAA tCAC tCAS
84ns 104ns
50ns 60ns
20ns 25ns
25ns 30ns
15ns 17ns
8ns 10ns
1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01
1
©2001, Micron Technology, Inc
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
16Mb: 1 MEG x16 EDO DRAM
GENERAL DESCRIPTION (continued)
of the two signals results in a BYTE WRITE cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered 10 bits (A0-A9) at a time. RAS# is used to latch the first 10 bits and CAS#, the latter 10 bits. The CAS# function also determines whether the cycle will be a refresh cycle (RAS# ONLY) or an active cycle (READ, WRITE or READ-WRITE) once RAS# goes LOW. The CASL# and CASH# inputs internally generate a CAS# signal that functions like the single CAS# input on other DRAMs. The key difference is each CAS# input (CASL# and CASH#) controls its corresponding eight DQ inputs during WRITE accesses. CASL# controls DQ0-DQ7, and CASH# controls DQ8-DQ15. The two CAS# controls give the 1 Meg x 16 both BYTE READ and BYTE WRITE cycle capabilities. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READ-MODIFYWRITE occurs when WE falls after CAS# (CASL# or CASH#) was taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READMODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direc.