DP84902

DP84902 1 7 Encoder Decoder Circuit June 1994 DP84902 1 7 Encoder Decoder Circuit General Description The DP84902 is designed to perform the encoding and decoding for disk memory systems It is designed to interface directly with Integrated Read Channel Products (such as National Semiconductor’s DP84910) and with Disk Data Controller Products with a 2-bit NRZ interface (such as National Semiconductor’s Advanced Disk Controllers) This Encoder Decoder (ENDEC) circuit employs a 2 3 (1 7) Run Length Limited (RLL) code type and supports the hard sectored format The DP84902 has the option of selecting either TTL or ECL compatible code output to interface with preamplifiers commonly used in high data rate applications This is accommplished by the setting of a bit in the control register The ENDEC also includes write data precompensation control circuitry which detects the need for write precompensation This circuitry issues early and late output signals necessary for precompensation The precompensation information is generated against a 2T pattern The precompensation circuitry can be bypassed by the setting of a bit in the control register A control reigster is included to configure the ENDEC and to select device operation options such as output code inversion differential code output bypassing of the encoder and the use of an internal write clock The DP84902 is available in 20-pin SO and 20-pin SSO packages Features Y Y Y Y Y Y Y Y Y Y Y Operates at 2-bit Non-Return to Zero...