Document
PRELIMINARY
MX28F2100B
2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY FEATURES
• 262,144x8/131,072x16 switchable • Fast access time: 70/90/120ns • Low power consumption – 50mA maximum active current – 100uA maximum standby current • Programming and erasing voltage 12V ± 7% • Command register architecture – Byte/Word Programming (50 us typical) – Auto chip erase 5 sec typical (including preprogramming time) – Block Erase (Any one from 5 blocks:16K-Byte x1, 8K-Byte x2, 96K-Byte x1, and 128K-Byte x1) – Auto Erase with Erase Suspend capability • Status Register feature for Device status detection • Auto Erase (chip & block) and Auto Program – Status Registers • 10,000 minimum erase/program cycles • Latch-up protected to 100mA from -1 to VCC+1V • Package type: – 44-pin SOP – 48-pin TSOP (Type 1)
GENERAL DESCRIPTION
The MX28F2100B is a 2-mega bit Flash memory organized as 256K bytes of 8 bits or 128K words of 16 bits switchable. MXIC's Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory. The MX28F2100B is packaged in 44-pin SOP and 48-pin TSOP(I). It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX28F2100B offers access times as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX28F2100B has separate chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX28F2100B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX28F2100B uses a 12.0V ± 7% VPP supply to perform the High Reliability Erase and auto Program/ Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
BLOCK STRUCTURE
A16~A0 1FFFFH 128 K-BYTE BLOCK 10000H 0FFFFH 96 K-BYTE BLOCK 04000H 03FFFH 03000H 02FFFH 02000H 01FFFH 00000H Word Mode (x16) Memor y Map *Byte Mode operation should include A-1(LSB) for addressing 8 K-BYTE BLOCK 8 K-BYTE BLOCK 16 K-BYTE BLOCK
P/N: PM0382
1
REV. 1.5, MAR. 24, 1998
MX28F2100B
PIN CONFIGURATIONS
44 SOP(500 mil)
VPP NC NC A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RP WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
TSOP (TYPE 1) (12mm x 20mm)
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RP VPP NC NC NC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
MX28F2100B
MX28F2100B
(NORMAL TYPE)
PIN DESCRIPTION:
SYMBOL A0~A16 Q0~Q14 Q15/A-1 CE WE BYTE RP OE VPP VCC GND PIN NAME Address Input Data Input/Output Q15(Word mode)/LSB addr(Byte mode) Chip Enable Input Write Enable Input Word/Byte Selction input Reset/Deep Power Down Output Enable Input Power supply for Program and Erase Power Supply Pin (+5V) Ground Pin
P/N: PM0382
REV. 1.5, MAR. 24, 1998
2
MX28F2100B
BLOCK DIAGRAM
CE OE WE BYTE RP
CONTROL INPUT LOGIC
PROGRAM/ERASE HIGH VOLTAGE
WRITE STATE MACHINE (WSM)
STATE
MX28F2100B
X-DECODER
REGISTER
ARRAY SOURCE HV
ADDRESS LATCH
Q15/A-1 A0-A16
FLASH ARRAY
AND BUFFER
Y-PASS GATE
COMMAND DATA DECODER
Y-DECODER
SENSE AMPLIFIER
PGM DATA HV
COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N: PM0382
REV. 1.5, MAR. 24, 1998
3
MX28F2100B
AUTOMATIC PROGRAMMING The MX28F2100B is byte/word programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical room temperature chip programming time of the MX28F2100B is less than 5 seconds. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to only write an Erase Set-up command and an Erase command. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. A status register provides feedback to the user as to the status of the erase operation. It is noted that after an Erase Set-up command, if the .