CY7C1231F

Features Can support up to 117-MHz bus operations with zero wait states — Data is transferred on every clock w w Pin compatible and functionally equivalent to ZBT™ devices Internally self-timed output buffer control to eliminate the need to use OE Registered inputs for flow-through operation Byte Write capability 128K x 18 common I/O architecture Single 3.3V power supply Fast clock-to-output times — 7.5 ns (for 117-MHz device) — 8.5 ns (for 100-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous Output Enable JEDEC-standard 100 TQFP package Low standby power Burst Capability—linear or interleaved burst order w .D at h S a ee U 4 t . m o c Functional Description[1] CY7C1231F 2-Mbit (128K x 18) Flow-through SRAM with NoBL™ Architecture The CY7C1231F is a 3.3V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231F is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) sig...