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MT58L512L18F Dataheets PDF



Part Number MT58L512L18F
Manufacturers Micron Semiconductor
Logo Micron Semiconductor
Description (MT58Lxxxx) 8Mb SYNCBURST SRAM
Datasheet MT58L512L18F DatasheetMT58L512L18F Datasheet (PDF)

. U 4 t ™ 8Mb SYNCBURST e e h SRAM S a t a D . FEATURES w w w m o c 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM MT58L512L18F, MT58L256L32F, MT58L256L36F; MT58L512V18F, MT58L256V32F, MT58L256V36F 3.3V VDD, 3.3V or 2.5V I/O, Flow-Through • Fast clock and OE# access times • Single +3.3V +0.3V/-0.165V power supply (VDD) • Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Individual BYTE WRITE c.

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. U 4 t ™ 8Mb SYNCBURST e e h SRAM S a t a D . FEATURES w w w m o c 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM MT58L512L18F, MT58L256L32F, MT58L256L36F; MT58L512V18F, MT58L256V32F, MT58L256V36F 3.3V VDD, 3.3V or 2.5V I/O, Flow-Through • Fast clock and OE# access times • Single +3.3V +0.3V/-0.165V power supply (VDD) • Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Individual BYTE WRITE control and GLOBAL WRITE • Three chip enables for simple depth expansion and address pipelining • Clock-controlled and registered addresses, data I/Os and control signals • Internally self-timed WRITE cycle • Burst control (interleaved or linear burst) • Automatic power-down for portable applications • 100-pin TQFP package • 165-pin FBGA • Low capacitive bus loading • x18, x32, and x36 versions available 100-Pin TQFP1 OPTIONS • Timing (Access/Cycle/MHz) 7.5ns/8.8ns/113 MHz 8.5ns/10ns/100 MHz 10ns/15ns/66 MHz • Configurations 3.3V I/O 512K x 18 256K x 32 256K x 36 2.5V I/O 512K x 18 256K x 32 256K x 36 • Packages 100-pin TQFP (2-chip enable) 100-pin TQFP (3-chip enable) 165-pin, 13mm x 15mm FBGA • Operating Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C)** MARKING w w w .D t a -7.5 -8.5 -10 T S F* None IT S a e h t e U 4 .c m o 165-Pin FBGA NOTE: 1. JEDEC-standard MS-026 BHA (LQFP). MT58L512L18F MT58L256L32F MT58L256L36F * A Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/support/index.html. ** Industrial temperature range offered in specific speed grades and configurations. Contact factory for more information. MT58L512V18F MT58L256V32F MT58L256V36F GENERAL DESCRIPTION Part Number Example: MT58L256V36FT-10 The Micron® SyncBurst™ SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2#, CE2), burst control inputs (ADSC#, ADSP#, ADV#), byte write 8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM MT58L512L18F_C.p65 – Rev. 2/02 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. w w w .D at h S a t e e 4U . m o c 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 512K X 18 19 SA0, SA1, SAs MODE ADV# CLK ADDRESS REGISTER 19 17 19 2 SA0-SA1 SA1' BINARY Q1 COUNTER AND LOGIC CLR Q0 SA0' ADSC# ADSP# BYTE “b” WRITE REGISTER BYTE “b” WRITE DRIVER 9 512K x 9 x 2 MEMORY ARRAY BYTE “a” WRITE DRIVER 9 18 SENSE AMPS 18 OUTPUT BUFFERS 18 DQs DQPa DQPb BWb# BWa# BWE# GW# CE# CE2 CE2# OE# BYTE “a” WRITE REGISTER ENABLE REGISTER 18 INPUT REGISTERS 2 FUNCTIONAL BLOCK DIAGRAM 256K X 32/36 18 SA0, SA1, SAs MODE ADV# CLK BINARY Q1 SA1' COUNTER AND LOGIC Q0 CLR SA0' ADDRESS REGISTER 18 SA0-SA1 16 18 ADSC# ADSP# BWd# BYTE “d” WRITE REGISTER BYTE “d” WRITE DRIVER 9 BWc# BYTE “c” WRITE REGISTER BYTE “c” WRITE DRIVER 9 256K x 8 x 4 (x32) 256K x 9 x 4 (x36) 36 SENSE AMPS 36 OUTPUT BUFFERS 36 BWb# BYTE “b” WRITE REGISTER BYTE “b” WRITE DRIVER 9 MEMORY ARRAY DQs DQPa DQPb DQPc DQPd BWa# BWE# GW# CE# CE2 CE2# OE# BYTE “a” WRITE REGISTER BYTE “a” WRITE DRIVER 9 36 ENABLE REGISTER 4 INPUT REGISTERS NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions, and timing diagrams for detailed information. 8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM MT58L512L18F_C.p65 – Rev. 2/02 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM GENERAL DESCRIPTION (continued) enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version. Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE.


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